coreplex: allow buffer chains on certain bus ports
This commit is contained in:
committed by
Wesley W. Terpstra
parent
57d0360c35
commit
3bde9506c6
@ -32,6 +32,7 @@ abstract class TLBusWrapper(params: TLBusParams, val busName: String)(implicit p
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protected val xbar = LazyModule(new TLXbar)
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xbar.suggestName(busName)
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private val master_buffer = LazyModule(new TLBuffer(masterBuffering))
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master_buffer.suggestName(s"${busName}_master_TLBuffer")
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private val slave_buffer = LazyModule(new TLBuffer(slaveBuffering))
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@ -66,6 +67,19 @@ abstract class TLBusWrapper(params: TLBusParams, val busName: String)(implicit p
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protected def inwardNode: TLInwardNode = xbar.node
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protected def inwardBufNode: TLInwardNode = master_buffer.node
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protected def bufferChain(n: Int, params: BufferParams = BufferParams.default, name: Option[String] = None): (TLInwardNode, TLOutwardNode) = {
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if (n > 0) {
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val chain = List.fill(n)(LazyModule(new TLBuffer(params)))
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name.foreach { n => chain.zipWithIndex foreach { case(b, i) => b.suggestName(s"${busName}_${n}_${i}_TLBuffer") } }
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(chain.init zip chain.tail) foreach { case(prev, next) => next.node :=* prev.node }
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(chain.head.node, chain.last.node)
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} else {
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val dummy = LazyModule(new TLBuffer(BufferParams.none))
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dummy.suggestName(s"${busName}_${n}_empty_TLBuffer")
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(dummy.node, dummy.node)
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}
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}
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def bufferFromMasters: TLInwardNode = inwardBufNode
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def bufferToSlaves: TLOutwardNode = outwardBufNode
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