riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

coreplex: allow buffer chains on certain bus ports

Browse Source
This commit is contained in:
Henry Cook
2017-08-30 17:57:52 -07:00
committed by Wesley W. Terpstra
parent 57d0360c35
commit 3bde9506c6
7 changed files with 74 additions and 53 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
src/main/scala/tile/RocketTile.scala
View File

@ -19,7 +19,8 @@ case class RocketTileParams(
btb: Option[BTBParams] = Some(BTBParams()),
dataScratchpadBytes: Int = 0,
boundaryBuffers: Boolean = false,
name: Option[String] = Some("tile")) extends TileParams {
name: Option[String] = Some("tile"),
externalBuffers: Int = 0) extends TileParams {
require(icache.isDefined)
require(dcache.isDefined)
}