riscv/rocket-chip
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Explicitely convert results of Bits Muxes to UInt

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Chisel updated to emit SInt result instead of UInt so this commit addresses this change.
This commit is contained in:
Stephen Twigg 2015-02-03 18:15:01 -08:00
parent 57340be72b
commit 3b3250339a
1 changed files with 1 additions and 1 deletions
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uncore/src/main/scala/cache.scala
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@ -145,7 +145,7 @@ class MetadataArray[T <: Metadata](makeRstVal: () => T) extends CacheModule {
val rst = rst_cnt < UInt(nSets) val rst = rst_cnt < UInt(nSets)
val waddr = Mux(rst, rst_cnt, io.write.bits.idx) val waddr = Mux(rst, rst_cnt, io.write.bits.idx)
val wdata = Mux(rst, rstVal, io.write.bits.data).toBits val wdata = Mux(rst, rstVal, io.write.bits.data).toBits
val wmask = Mux(rst, SInt(-1), io.write.bits.way_en) val wmask = Mux(rst, SInt(-1), io.write.bits.way_en).toUInt
when (rst) { rst_cnt := rst_cnt+UInt(1) } when (rst) { rst_cnt := rst_cnt+UInt(1) }
val tag_arr = Mem(UInt(width = metabits*nWays), nSets, seqRead = true) val tag_arr = Mem(UInt(width = metabits*nWays), nSets, seqRead = true)