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tilelink: better address masking for fuzzing

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This commit is contained in:
Henry Cook 2017-05-08 18:48:40 -07:00
parent 9720a53eae
commit 3af40bff8b
1 changed files with 3 additions and 3 deletions
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6
src/main/scala/uncore/tilelink2/Fuzzer.scala
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@ -97,11 +97,10 @@ class TLFuzzer(
val edge = node.edgesOut(0) val edge = node.edgesOut(0)
// Extract useful parameters from the TL edge // Extract useful parameters from the TL edge
val endAddress = overrideAddress.map(_.max).getOrElse(edge.manager.maxAddress)
val maxTransfer = edge.manager.maxTransfer val maxTransfer = edge.manager.maxTransfer
val beatBytes = edge.manager.beatBytes val beatBytes = edge.manager.beatBytes
val maxLgBeats = log2Up(maxTransfer/beatBytes) val maxLgBeats = log2Up(maxTransfer/beatBytes)
val addressBits = log2Up(endAddress) val addressBits = log2Up(overrideAddress.map(_.max).getOrElse(edge.manager.maxAddress))
val sizeBits = edge.bundle.sizeBits val sizeBits = edge.bundle.sizeBits
val dataBits = edge.bundle.dataBits val dataBits = edge.bundle.dataBits
@ -137,7 +136,8 @@ class TLFuzzer(
val log_op = noiseMaker(2, inc, 0) val log_op = noiseMaker(2, inc, 0)
val amo_size = UInt(2) + noiseMaker(1, inc, 0) // word or dword val amo_size = UInt(2) + noiseMaker(1, inc, 0) // word or dword
val size = noiseMaker(sizeBits, inc, 0) val size = noiseMaker(sizeBits, inc, 0)
val addr = noiseMaker(addressBits, inc, 2) & ~UIntToOH1(size, addressBits) val addrMask = overrideAddress.map(_.max.U).getOrElse(~UInt(0, addressBits))
val addr = noiseMaker(addressBits, inc, 2) & ~UIntToOH1(size, addressBits) & addrMask
val mask = noiseMaker(beatBytes, inc_beat, 2) & edge.mask(addr, size) val mask = noiseMaker(beatBytes, inc_beat, 2) & edge.mask(addr, size)
val data = noiseMaker(dataBits, inc_beat, 2) val data = noiseMaker(dataBits, inc_beat, 2)