diff --git a/rocket/src/main/scala/dpath_util.scala b/rocket/src/main/scala/dpath_util.scala index 5583d6ed..3e4fe3d2 100644 --- a/rocket/src/main/scala/dpath_util.scala +++ b/rocket/src/main/scala/dpath_util.scala @@ -120,14 +120,14 @@ class rocketDpathPCR extends Component val rdata = Wire() { Bits() }; - val ren = io.r.en || io.host.pcr_ren - val raddr = Mux(io.r.en, io.r.addr, io.host.pcr_addr) - io.host.pcr_rdata := rdata + val raddr = Mux(io.r.en, io.r.addr, io.host.pcr_req.bits.addr) + io.host.pcr_rep.valid := io.host.pcr_req.valid && !io.r.en && !io.host.pcr_req.bits.rw + io.host.pcr_rep.bits := rdata - val wen = io.w.en || io.host.pcr_wen - val waddr = Mux(io.w.en, io.w.addr, io.host.pcr_addr) - val wdata = Mux(io.w.en, io.w.data, io.host.pcr_wdata) - io.host.pcr_rdy := Mux(io.host.pcr_wen, !io.w.en, !io.r.en) + val wen = io.w.en || io.host.pcr_req.valid && io.host.pcr_req.bits.rw + val waddr = Mux(io.w.en, io.w.addr, io.host.pcr_req.bits.addr) + val wdata = Mux(io.w.en, io.w.data, io.host.pcr_req.bits.data) + io.host.pcr_req.ready := Mux(io.host.pcr_req.bits.rw, !io.w.en, !io.r.en) io.ptbr_wen := reg_status_vm.toBool && wen && (waddr === PCR_PTBR); io.status := Cat(reg_status_im, Bits(0,7), reg_status_vm, reg_status_sx, reg_status_ux, reg_status_s, reg_status_ps, reg_status_ec, reg_status_ev, reg_status_ef, reg_status_et); @@ -203,26 +203,23 @@ class rocketDpathPCR extends Component when (waddr === PCR_VECBANK) { reg_vecbank:= wdata(7,0) } } - rdata := Bits(0, 64) - when (ren) { - switch (raddr) { - is (PCR_STATUS) { rdata := io.status } - is (PCR_EPC) { rdata := Cat(Fill(64-VADDR_BITS-1, reg_epc(VADDR_BITS)), reg_epc); } - is (PCR_BADVADDR) { rdata := Cat(Fill(64-VADDR_BITS-1, reg_badvaddr(VADDR_BITS)), reg_badvaddr); } - is (PCR_EVEC) { rdata := Cat(Fill(64-VADDR_BITS, reg_ebase(VADDR_BITS-1)), reg_ebase); } - is (PCR_COUNT) { rdata := Cat(Fill(32, reg_count(31)), reg_count); } - is (PCR_COMPARE) { rdata := Cat(Fill(32, reg_compare(31)), reg_compare); } - is (PCR_CAUSE) { rdata := Cat(reg_cause(5), Bits(0,58), reg_cause(4,0)); } - is (PCR_COREID) { rdata := Bits(COREID,64); } - is (PCR_IMPL) { rdata := Bits(2) } - is (PCR_FROMHOST) { rdata := reg_fromhost; } - is (PCR_TOHOST) { rdata := reg_tohost; } - is (PCR_K0) { rdata := reg_k0; } - is (PCR_K1) { rdata := reg_k1; } - is (PCR_PTBR) { rdata := Cat(Bits(0,64-PADDR_BITS), reg_ptbr); } - is (PCR_VECBANK) { rdata := Cat(Bits(0, 56), reg_vecbank) } - is (PCR_VECCFG) { rdata := Cat(Bits(0, 40), io.vec_nfregs, io.vec_nxregs, io.vec_appvl) } - } + rdata := io.status // raddr === PCR_STATUS + switch (raddr) { + is (PCR_EPC) { rdata := Cat(Fill(64-VADDR_BITS-1, reg_epc(VADDR_BITS)), reg_epc); } + is (PCR_BADVADDR) { rdata := Cat(Fill(64-VADDR_BITS-1, reg_badvaddr(VADDR_BITS)), reg_badvaddr); } + is (PCR_EVEC) { rdata := Cat(Fill(64-VADDR_BITS, reg_ebase(VADDR_BITS-1)), reg_ebase); } + is (PCR_COUNT) { rdata := Cat(Fill(32, reg_count(31)), reg_count); } + is (PCR_COMPARE) { rdata := Cat(Fill(32, reg_compare(31)), reg_compare); } + is (PCR_CAUSE) { rdata := Cat(reg_cause(5), Bits(0,58), reg_cause(4,0)); } + is (PCR_COREID) { rdata := Bits(COREID,64); } + is (PCR_IMPL) { rdata := Bits(2) } + is (PCR_FROMHOST) { rdata := reg_fromhost; } + is (PCR_TOHOST) { rdata := reg_tohost; } + is (PCR_K0) { rdata := reg_k0; } + is (PCR_K1) { rdata := reg_k1; } + is (PCR_PTBR) { rdata := Cat(Bits(0,64-PADDR_BITS), reg_ptbr); } + is (PCR_VECBANK) { rdata := Cat(Bits(0, 56), reg_vecbank) } + is (PCR_VECCFG) { rdata := Cat(Bits(0, 40), io.vec_nfregs, io.vec_nxregs, io.vec_appvl) } } } diff --git a/rocket/src/main/scala/htif.scala b/rocket/src/main/scala/htif.scala index a5c6cd0a..b29d095a 100644 --- a/rocket/src/main/scala/htif.scala +++ b/rocket/src/main/scala/htif.scala @@ -10,15 +10,18 @@ class ioHost(w: Int, view: List[String] = null) extends Bundle(view) val out = new ioDecoupled()(Bits(width = w)) } +class PCRReq extends Bundle +{ + val rw = Bool() + val addr = Bits(width = 5) + val data = Bits(width = 64) +} + class ioHTIF extends Bundle { val reset = Bool(INPUT) - val pcr_wen = Bool(INPUT) - val pcr_ren = Bool(INPUT) - val pcr_rdy = Bool(OUTPUT) - val pcr_addr = Bits(5, INPUT) - val pcr_wdata = Bits(64, INPUT) - val pcr_rdata = Bits(64, OUTPUT) + val pcr_req = (new ioDecoupled) { new PCRReq }.flip + val pcr_rep = (new ioPipe) { Bits(width = 64) } } class rocketHTIF(w: Int, ncores: Int) extends Component with FourStateCoherence @@ -170,27 +173,30 @@ class rocketHTIF(w: Int, ncores: Int) extends Component with FourStateCoherence pcr_done := Bool(false) val pcr_mux = (new Mux1H(ncores)) { Bits(width = 64) } for (i <- 0 until ncores) { - val me = pcr_coreid === UFix(i) - io.cpu(i).pcr_wen := Reg(state === state_pcr && cmd === cmd_writecr && me, resetVal = Bool(false)) - io.cpu(i).pcr_addr := Reg(pcr_addr) - io.cpu(i).pcr_wdata := Reg(pcr_wdata) - val my_reset = Reg(resetVal = Bool(true)) - when (io.cpu(i).pcr_wen && io.cpu(i).pcr_rdy) { - when (io.cpu(i).pcr_addr === PCR_RESET) { my_reset := io.cpu(i).pcr_wdata(0) } - pcr_done := Bool(true) - } - io.cpu(i).reset := my_reset - - io.cpu(i).pcr_ren := Reg(state === state_pcr && cmd === cmd_readcr && me, resetVal = Bool(false)) val rdata = Reg() { Bits() } - when (io.cpu(i).pcr_ren && io.cpu(i).pcr_rdy) { - rdata := io.cpu(i).pcr_rdata - when (io.cpu(i).pcr_addr === PCR_RESET) { rdata := my_reset } + + val cpu = io.cpu(i) + val me = pcr_coreid === UFix(i) + cpu.pcr_req.valid := state === state_pcr && me + cpu.pcr_req.bits.rw := cmd === cmd_writecr + cpu.pcr_req.bits.addr := pcr_addr + cpu.pcr_req.bits.data := pcr_wdata + cpu.reset := my_reset + + when (cpu.pcr_req.valid && cpu.pcr_req.ready && cpu.pcr_req.bits.rw) { pcr_done := Bool(true) + when (cpu.pcr_req.bits.addr === PCR_RESET) { + my_reset := cpu.pcr_req.bits.data(0) + } } - pcr_mux.io.sel(i) := Reg(me) - pcr_mux.io.in(i) := rdata + when (cpu.pcr_rep.valid) { + pcr_done := Bool(true) + rdata := cpu.pcr_rep.bits + } + + pcr_mux.io.sel(i) := me + pcr_mux.io.in(i) := Mux(pcr_addr === PCR_RESET, my_reset, rdata) } val tx_cmd = Mux(nack, cmd_nack, cmd_ack)