diff --git a/junctions/src/main/scala/hasti.scala b/junctions/src/main/scala/hasti.scala
index 00c4c963..7b3380ac 100644
--- a/junctions/src/main/scala/hasti.scala
+++ b/junctions/src/main/scala/hasti.scala
@@ -74,7 +74,7 @@ class HASTIBus(amap: Seq[UInt=>Bool]) extends Module
 {
   val io = new Bundle {
     val master = new HASTIMasterIO().flip
-    val slaves = Vec.fill(amap.size){new HASTISlaveIO}.flip
+    val slaves = Vec(new HASTISlaveIO, amap.size).flip
   }
 
   // skid buffer
@@ -215,8 +215,8 @@ class HASTISlaveMux(n: Int) extends Module
 class HASTIXbar(nMasters: Int, addressMap: Seq[UInt=>Bool]) extends Module
 {
   val io = new Bundle {
-    val masters = Vec.fill(nMasters){new HASTIMasterIO}.flip
-    val slaves = Vec.fill(addressMap.size){new HASTISlaveIO}.flip
+    val masters = Vec(new HASTIMasterIO, nMasters).flip
+    val slaves = Vec(new HASTISlaveIO, addressMap.size).flip
   }
 
   val buses = List.fill(nMasters){Module(new HASTIBus(addressMap))}
diff --git a/junctions/src/main/scala/memserdes.scala b/junctions/src/main/scala/memserdes.scala
index bb92690c..78212952 100644
--- a/junctions/src/main/scala/memserdes.scala
+++ b/junctions/src/main/scala/memserdes.scala
@@ -265,7 +265,7 @@ object HellaQueue
 
 class MemIOArbiter(val arbN: Int) extends MIFModule {
   val io = new Bundle {
-    val inner = Vec.fill(arbN){new MemIO}.flip
+    val inner = Vec(new MemIO, arbN).flip
     val outer = new MemIO
   }
 
diff --git a/junctions/src/main/scala/poci.scala b/junctions/src/main/scala/poci.scala
index f6eaece2..bfd581c7 100644
--- a/junctions/src/main/scala/poci.scala
+++ b/junctions/src/main/scala/poci.scala
@@ -66,7 +66,7 @@ class POCIBus(amap: Seq[UInt=>Bool]) extends Module
 {
   val io = new Bundle {
     val master = new POCIIO().flip
-    val slaves = Vec.fill(amap.size){new POCIIO}
+    val slaves = Vec(new POCIIO, amap.size)
   }
 
   val psels = PriorityEncoderOH(