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debug: use a different form of the crossing which doesn't create an AsyncScope (#394)

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mwachs5 2016-10-09 20:33:18 -07:00 committed by GitHub
parent b5d4b72313
commit 3a1d8fe482
1 changed files with 2 additions and 11 deletions
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13
src/main/scala/rocketchip/DebugTransport.scala
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@ -1,7 +1,7 @@
package rocketchip package rocketchip
import Chisel._ import Chisel._
import uncore.devices.{DebugBusIO, AsyncDebugBusTo, AsyncDebugBusFrom, DebugBusReq, DebugBusResp, DMKey} import uncore.devices.{DebugBusIO, AsyncDebugBusCrossing, DebugBusReq, DebugBusResp, DMKey}
import junctions._ import junctions._
import util._ import util._
import cde.{Parameters, Field} import cde.{Parameters, Field}
@ -62,7 +62,7 @@ class JtagDTMWithSync(depth: Int = 1, sync: Int = 3)(implicit val p: Parameters)
val io_debug_bus = Wire (new DebugBusIO) val io_debug_bus = Wire (new DebugBusIO)
io.debug <> AsyncDebugBusFrom(io.jtag.TCK, io.jtag.TRST, io_debug_bus, depth, sync) io.debug <> AsyncDebugBusCrossing(io.jtag.TCK, io.jtag.TRST, io_debug_bus, clock, reset, depth, sync)
// Translate from straight 'bits' interface of the blackboxes // Translate from straight 'bits' interface of the blackboxes
// into the Resp/Req data structures. // into the Resp/Req data structures.
@ -90,12 +90,3 @@ class DebugTransportModuleJtag(reqSize : Int, respSize : Int)(implicit val p: Pa
} }
} }
class AsyncMailbox extends BlackBox {
// This Verilog module is parameterized, but until this is supported by Chisel,
// this mailbox just has a fixed width of 64 bits, which is enough
// for our specific purpose here.
val io = new CrossingIO(UInt(width=64))
}