riscv/rocket-chip
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don't take interrupts while they're disabled!

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a control bug allowed an interrupt to be taken on the instruction immediately
following an interrupt-disabling instruction (but not thereafter).
This commit is contained in:
Andrew Waterman 2013-05-19 23:27:47 -07:00
parent 6eb4c2542a
commit 3a1b5f01b2
1 changed files with 1 additions and 1 deletions
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rocket/src/main/scala/ctrl.scala
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@ -530,7 +530,7 @@ class Control(implicit conf: RocketConfiguration) extends Component
(ex_reg_fp_val && io.fpu.illegal_rm, UFix(2)))) (ex_reg_fp_val && io.fpu.illegal_rm, UFix(2))))
mem_reg_replay := replay_ex && !take_pc_wb; mem_reg_replay := replay_ex && !take_pc_wb;
mem_reg_xcpt_interrupt := ex_reg_xcpt_interrupt && !take_pc_wb mem_reg_xcpt_interrupt := ex_reg_xcpt_interrupt && !take_pc_wb && !mem_reg_replay_next
when (ex_xcpt) { mem_reg_cause := ex_cause } when (ex_xcpt) { mem_reg_cause := ex_cause }
mem_reg_div_mul_val := ex_reg_div_mul_val && io.dpath.div_mul_rdy mem_reg_div_mul_val := ex_reg_div_mul_val && io.dpath.div_mul_rdy