fixes to exception and dcache miss/blocked handling
This commit is contained in:
Rimas Avizienis
parent
7a528d6255
commit
3a02028a35
@ -56,8 +56,6 @@ class ioCtrlDpath extends Bundle()
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val wb_waddr = UFix(5,'input); // write addr from writeback stage
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val exception = Bool('input);
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val status = Bits(8, 'input);
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// val sboard_set = Bool('input);
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// val sboard_seta = UFix(5, 'input);
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val sboard_clr0 = Bool('input);
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val sboard_clr0a = UFix(5, 'input);
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val sboard_clr1 = Bool('input);
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@ -215,9 +213,6 @@ class rocketCtrl extends Component
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sboard.io.raddrb := id_raddr1.toUFix;
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sboard.io.raddrc := id_waddr.toUFix;
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// sboard.io.set := io.dpath.sboard_set;
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// sboard.io.seta := io.dpath.sboard_seta;
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// scoreboard set (for D$ misses, div, mul)
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sboard.io.set := wb_reg_div_mul_val | dcache_miss;
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sboard.io.seta := io.dpath.wb_waddr;
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@ -298,21 +293,27 @@ class rocketCtrl extends Component
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io.dmem.req_type := ex_reg_mem_type;
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val mem_reg_div_mul_val = Reg(){Bool()};
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val mem_reg_eret = Reg(){Bool()};
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val mem_reg_mem_val = Reg(){Bool()};
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val mem_reg_mem_cmd = Reg(){UFix(width = 4)};
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val mem_reg_mem_type = Reg(){UFix(width = 3)};
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val mem_reg_privileged = Reg(){Bool()};
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when (reset.toBool || io.dpath.killx) {
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mem_reg_div_mul_val <== Bool(false);
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mem_reg_eret <== Bool(false);
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mem_reg_mem_val <== Bool(false);
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mem_reg_mem_cmd <== UFix(0, 4);
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mem_reg_mem_type <== UFix(0, 3);
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mem_reg_privileged <== Bool(false);
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}
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otherwise {
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mem_reg_div_mul_val <== ex_reg_div_mul_val;
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mem_reg_eret <== ex_reg_eret;
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mem_reg_mem_val <== ex_reg_mem_val;
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mem_reg_mem_cmd <== ex_reg_mem_cmd;
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mem_reg_mem_type <== ex_reg_mem_type;
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mem_reg_privileged <== ex_reg_privileged;
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}
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when (reset.toBool || io.dpath.killm) {
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@ -327,7 +328,9 @@ class rocketCtrl extends Component
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// replay PC+4 on a D$ load miss
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val mem_cmd_load = mem_reg_mem_val && (mem_reg_mem_cmd === M_XRD);
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val replay_mem_pc_plus4 = mem_cmd_load && !io.dmem.resp_val;
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val replay_mem = replay_mem_pc | replay_mem_pc_plus4;
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val kill_ex = replay_mem_pc | replay_mem_pc_plus4 | mem_reg_privileged | io.dpath.exception;
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val kill_mem = io.dpath.exception;
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dcache_miss <== replay_mem_pc_plus4;
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@ -336,10 +339,11 @@ class rocketCtrl extends Component
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io.dpath.sel_pc :=
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Mux(replay_mem_pc, PC_MEM,
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Mux(replay_mem_pc_plus4, PC_MEM4,
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Mux(io.dpath.exception || ex_reg_eret, PC_PCR,
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Mux(replay_mem_pc_plus4 || mem_reg_privileged, PC_MEM4,
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Mux(io.dpath.exception || mem_reg_eret, PC_PCR,
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Mux(!ex_reg_btb_hit && br_taken, PC_BR,
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Mux(ex_reg_btb_hit && !br_taken || ex_reg_privileged, PC_EX4,
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Mux(ex_reg_btb_hit && !br_taken, PC_EX4,
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// Mux(ex_reg_btb_hit && !br_taken || ex_reg_privileged, PC_EX4,
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Mux(jr_taken, PC_JR,
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Mux(j_taken, PC_J,
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Mux(io.dpath.btb_hit, PC_BTB,
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@ -353,8 +357,8 @@ class rocketCtrl extends Component
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jr_taken |
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j_taken |
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io.dpath.exception |
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ex_reg_privileged |
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ex_reg_eret |
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mem_reg_privileged |
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mem_reg_eret |
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replay_mem_pc |
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replay_mem_pc_plus4;
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@ -369,15 +373,10 @@ class rocketCtrl extends Component
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// check for loads in execute and mem stages to detect load/use hazards
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val ex_mem_cmd_load = ex_reg_mem_val && (ex_reg_mem_cmd === M_XRD);
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val lu_stall_raddr1_ex =
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val lu_stall_ex =
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ex_mem_cmd_load &&
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id_ren1.toBool &&
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(id_raddr1 === io.dpath.ex_waddr);
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val lu_stall_raddr2_ex =
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ex_mem_cmd_load &&
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id_ren2.toBool &&
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(id_raddr2 === io.dpath.ex_waddr);
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((id_ren1.toBool && (id_raddr1 === io.dpath.ex_waddr)) ||
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(id_ren2.toBool && (id_raddr2 === io.dpath.ex_waddr)));
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val mem_mem_cmd_load_bh =
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mem_reg_mem_val &&
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@ -387,15 +386,12 @@ class rocketCtrl extends Component
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(mem_reg_mem_type === MT_H) ||
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(mem_reg_mem_type === MT_HU));
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val lu_stall_raddr1_mem =
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val lu_stall_mem =
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mem_mem_cmd_load_bh &&
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id_ren1.toBool &&
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(id_raddr1 === io.dpath.mem_waddr);
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((id_ren1.toBool && (id_raddr1 === io.dpath.mem_waddr)) ||
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(id_ren2.toBool && (id_raddr2 === io.dpath.mem_waddr)));
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val lu_stall_raddr2_mem =
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mem_mem_cmd_load_bh &&
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id_ren2.toBool &&
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(id_raddr2 === io.dpath.mem_waddr);
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val lu_stall = lu_stall_ex || lu_stall_mem;
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// check for divide and multiply instructions in ex,mem,wb stages
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val dm_stall_ex =
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@ -419,19 +415,13 @@ class rocketCtrl extends Component
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~take_pc &
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(
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dm_stall |
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lu_stall_raddr1_ex |
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lu_stall_raddr2_ex |
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lu_stall_raddr1_mem |
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lu_stall_raddr2_mem |
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lu_stall |
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id_ren2 & id_stall_raddr2 |
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id_ren1 & id_stall_raddr1 |
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(id_sel_wa === WA_RD) && id_stall_waddr |
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(id_sel_wa === WA_RD) & id_stall_waddr |
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(id_sel_wa === WA_RA) & id_stall_ra |
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id_mem_val & ~io.dmem.req_rdy |
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id_sync & ~io.dmem.req_rdy |
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// id_mem_val_masked & id_full_mrq |
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// id_sync & (~id_empty_mrq | io.mem.dc_busy) |
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// mem_xstore_val & ~io.mem.xsdq_rdy |
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id_console_out_val & ~io.console.rdy |
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id_div_val & ~io.dpath.div_rdy |
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io.dpath.div_result_val |
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@ -448,8 +438,8 @@ class rocketCtrl extends Component
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io.dpath.killf := take_pc | ~io.imem.resp_val;
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io.dpath.killd := ctrl_killd.toBool;
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io.dpath.killx := replay_mem.toBool;
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io.dpath.killm := replay_mem.toBool;
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io.dpath.killx := kill_ex.toBool;
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io.dpath.killm := kill_mem.toBool;
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io.dpath.ren2 := id_ren2.toBool;
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io.dpath.ren1 := id_ren1.toBool;
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@ -76,23 +76,28 @@ class rocketDpath extends Component
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val ex_wdata = Wire() { Bits() };
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// memory definitions
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val mem_reg_pc = Reg(resetVal = UFix(0,32));
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val mem_reg_pc_plus4 = Reg(resetVal = UFix(0,32));
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val mem_reg_waddr = Reg(resetVal = UFix(0,5));
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val mem_reg_wdata = Reg(resetVal = Bits(0,64));
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val mem_reg_raddr2 = Reg(resetVal = UFix(0,5));
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val mem_reg_ctrl_ll_wb = Reg(resetVal = Bool(false));
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val mem_reg_pc = Reg(resetVal = UFix(0,32));
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val mem_reg_pc_plus4 = Reg(resetVal = UFix(0,32));
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val mem_reg_waddr = Reg(resetVal = UFix(0,5));
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val mem_reg_wdata = Reg(resetVal = Bits(0,64));
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val mem_reg_raddr2 = Reg(resetVal = UFix(0,5));
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val mem_reg_pcr = Reg(resetVal = Bits(0,64));
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val mem_reg_ctrl_cause = Reg(resetVal = UFix(0,5));
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val mem_reg_ctrl_eret = Reg(resetVal = Bool(false));
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val mem_reg_ctrl_exception = Reg(resetVal = Bool(false));
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val mem_reg_ctrl_ll_wb = Reg(resetVal = Bool(false));
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val mem_reg_ctrl_wen = Reg(resetVal = Bool(false));
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val mem_reg_ctrl_wen_pcr = Reg(resetVal = Bool(false));
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val mem_reg_ctrl_exception = Reg(resetVal = Bool(false));
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// writeback definitions
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val wb_reg_pc = Reg(resetVal = UFix(0,32));
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val wb_reg_pc_plus4 = Reg(resetVal = UFix(0,32));
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val wb_reg_waddr = Reg(resetVal = UFix(0,5));
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val wb_reg_wdata = Reg(resetVal = Bits(0,64));
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val wb_reg_ctrl_ll_wb = Reg(resetVal = Bool(false));
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val wb_reg_raddr2 = Reg(resetVal = UFix(0,5));
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val wb_reg_ctrl_cause = Reg(resetVal = UFix(0,5));
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val wb_reg_ctrl_eret = Reg(resetVal = Bool(false));
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val wb_reg_ctrl_exception = Reg(resetVal = Bool(false));
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val wb_reg_ctrl_wen = Reg(resetVal = Bool(false));
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val wb_reg_ctrl_wen_pcr = Reg(resetVal = Bool(false));
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@ -125,7 +130,7 @@ class rocketDpath extends Component
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Mux(io.ctrl.sel_pc === PC_BR, ex_branch_target,
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Mux(io.ctrl.sel_pc === PC_J, ex_branch_target,
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Mux(io.ctrl.sel_pc === PC_JR, ex_jr_target.toUFix,
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Mux(io.ctrl.sel_pc === PC_PCR, ex_pcr(31,0).toUFix,
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Mux(io.ctrl.sel_pc === PC_PCR, mem_reg_pcr(31,0).toUFix,
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Mux(io.ctrl.sel_pc === PC_MEM, mem_reg_pc,
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Mux(io.ctrl.sel_pc === PC_MEM4, mem_reg_pc_plus4,
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UFix(0, 32))))))))));
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@ -336,10 +341,10 @@ class rocketDpath extends Component
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pcr.io.host.from ^^ io.host.from;
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pcr.io.host.to ^^ io.host.to;
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pcr.io.eret := ex_reg_ctrl_eret;
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pcr.io.exception := ex_reg_ctrl_exception;
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pcr.io.cause := ex_reg_ctrl_cause;
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pcr.io.pc := ex_reg_pc;
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// pcr.io.eret := ex_reg_ctrl_eret;
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// pcr.io.exception := ex_reg_ctrl_exception;
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// pcr.io.cause := ex_reg_ctrl_cause;
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// pcr.io.pc := ex_reg_pc;
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io.ctrl.status := pcr.io.status;
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io.debug.error_mode := pcr.io.debug.error_mode;
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@ -363,17 +368,21 @@ class rocketDpath extends Component
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// memory stage
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mem_reg_pc <== ex_reg_pc;
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mem_reg_pc_plus4 <== ex_reg_pc_plus4;
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mem_reg_pcr <== ex_pcr;
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mem_reg_waddr <== ex_reg_waddr;
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mem_reg_wdata <== ex_wdata;
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mem_reg_ctrl_ll_wb <== ex_reg_ctrl_ll_wb;
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mem_reg_raddr2 <== ex_reg_raddr2;
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mem_reg_ctrl_cause <== ex_reg_ctrl_cause;
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when (io.ctrl.killx) {
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mem_reg_ctrl_eret <== Bool(false);
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mem_reg_ctrl_wen <== Bool(false);
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mem_reg_ctrl_wen_pcr <== Bool(false);
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mem_reg_ctrl_exception <== Bool(false);
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}
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otherwise {
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mem_reg_ctrl_eret <== ex_reg_ctrl_eret;
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mem_reg_ctrl_wen <== ex_reg_ctrl_wen;
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mem_reg_ctrl_wen_pcr <== ex_reg_ctrl_wen_pcr;
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mem_reg_ctrl_exception <== ex_reg_ctrl_exception;
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@ -384,14 +393,7 @@ class rocketDpath extends Component
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// for load/use hazard detection (load byte/halfword)
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io.ctrl.mem_waddr := mem_reg_waddr;
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// moved to earlier in file
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// val mem_dmem_resp_data_w =
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// Mux(io.dmem.resp_pos(2).toBool, io.dmem.resp_data(63, 32), io.dmem.resp_data(31, 0));
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//
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// val mem_dmem_resp_data =
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// Mux(io.dmem.resp_type === MT_D, io.dmem.resp_data,
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// Mux(io.dmem.resp_type === MT_W, Cat(Fill(32, mem_dmem_resp_data_w(31)), mem_dmem_resp_data_w)),
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// Cat(UFix(0,32), mem_dmem_resp_data_w));
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// 32/64 bit load handling (moved to earlier in file)
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// writeback stage
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r_dmem_resp_val <== io.dmem.resp_val;
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@ -400,12 +402,14 @@ class rocketDpath extends Component
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r_dmem_resp_type <== dmem_resp_type;
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r_dmem_resp_data <== mem_dmem_resp_data;
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wb_reg_pc <== mem_reg_pc;
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wb_reg_pc_plus4 <== mem_reg_pc_plus4;
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wb_reg_waddr <== mem_reg_waddr;
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wb_reg_wdata <== mem_reg_wdata;
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wb_reg_ctrl_ll_wb <== mem_reg_ctrl_ll_wb;
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wb_reg_raddr2 <== mem_reg_raddr2;
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wb_reg_pc <== mem_reg_pc;
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wb_reg_waddr <== mem_reg_waddr;
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wb_reg_wdata <== mem_reg_wdata;
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wb_reg_ctrl_ll_wb <== mem_reg_ctrl_ll_wb;
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wb_reg_raddr2 <== mem_reg_raddr2;
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wb_reg_ctrl_cause <== mem_reg_ctrl_cause;
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wb_reg_ctrl_eret <== mem_reg_ctrl_eret;
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wb_reg_ctrl_exception <== mem_reg_ctrl_exception;
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when (io.ctrl.killm) {
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wb_reg_ctrl_wen <== Bool(false);
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@ -416,21 +420,7 @@ class rocketDpath extends Component
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wb_reg_ctrl_wen_pcr <== mem_reg_ctrl_wen_pcr;
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}
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// crossbar/sign extension for 8/16 bit loads
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// val dmem_resp_data_h =
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// Mux(r_dmem_resp_pos(1).toBool, r_dmem_resp_data(31, 16), r_dmem_resp_data(15, 0));
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// val dmem_resp_data_b =
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// Mux(r_dmem_resp_pos(0).toBool, dmem_resp_data_h(15, 8), dmem_resp_data_h(7, 0));
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//
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// val dmem_resp_data_final =
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// Mux(r_dmem_resp_type === MT_B, Cat(Fill(56, dmem_resp_data_b(7)), dmem_resp_data_b),
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// Mux(r_dmem_resp_type === MT_BU, Cat(UFix(0, 56), dmem_resp_data_b),
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// Mux(r_dmem_resp_type === MT_H, Cat(Fill(48, dmem_resp_data_h(15)), dmem_resp_data_h),
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// Mux(r_dmem_resp_type === MT_HU, Cat(UFix(0, 48), dmem_resp_data_h),
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// Mux((r_dmem_resp_type === MT_W) ||
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// (r_dmem_resp_type === MT_WU) ||
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// (r_dmem_resp_type === MT_D), r_dmem_resp_data,
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// UFix(0,64))))));
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// crossbar/sign extension for 8/16 bit loads (moved to earlier in file)
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// regfile write
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rfile.io.w0.addr := wb_reg_waddr;
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@ -454,6 +444,11 @@ class rocketDpath extends Component
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pcr.io.w.en := wb_reg_ctrl_wen_pcr;
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pcr.io.w.data := wb_reg_wdata;
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pcr.io.eret := wb_reg_ctrl_eret;
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pcr.io.exception := wb_reg_ctrl_exception;
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pcr.io.cause := wb_reg_ctrl_cause;
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pcr.io.pc := wb_reg_pc;
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}
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}
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