From 39ec927a3f6f47a0b41855f746c7faed24b0c7c7 Mon Sep 17 00:00:00 2001 From: Howard Mao Date: Tue, 28 Jun 2016 18:30:11 -0700 Subject: [PATCH] replace complicated pattern substitutions with automatic variable --- regression/Makefile | 34 +++++++++++++++++----------------- vsim/Makefrag-verilog | 4 ++-- 2 files changed, 19 insertions(+), 19 deletions(-) diff --git a/regression/Makefile b/regression/Makefile index 804766bc..c4c8eff2 100644 --- a/regression/Makefile +++ b/regression/Makefile @@ -124,88 +124,88 @@ $(RISCV)/install.stamp: # Builds the various simulators stamps/%/emulator-verilog.stamp: stamps/other-submodules.stamp $(RISCV)/install.stamp mkdir -p $(dir $@) - +flock -x $(dir $@)/chisel-lock $(MAKE) -C $(abspath $(TOP))/emulator CONFIG=$(patsubst stamps/%/emulator-verilog.stamp,%,$@) RISCV=$(abspath $(RISCV)) CHISEL_VERSION=$(CHISEL_VERSION) verilog + +flock -x $(dir $@)/chisel-lock $(MAKE) -C $(abspath $(TOP))/emulator CONFIG=$* RISCV=$(abspath $(RISCV)) CHISEL_VERSION=$(CHISEL_VERSION) verilog date > $@ stamps/%/emulator-ndebug.stamp: stamps/other-submodules.stamp $(RISCV)/install.stamp mkdir -p $(dir $@) - +flock -x $(dir $@)/chisel-lock $(MAKE) -C $(abspath $(TOP))/emulator CONFIG=$(patsubst stamps/%/emulator-ndebug.stamp,%,$@) RISCV=$(abspath $(RISCV)) CHISEL_VERSION=$(CHISEL_VERSION) + +flock -x $(dir $@)/chisel-lock $(MAKE) -C $(abspath $(TOP))/emulator CONFIG=$* RISCV=$(abspath $(RISCV)) CHISEL_VERSION=$(CHISEL_VERSION) date > $@ stamps/%/emulator-debug.stamp: stamps/other-submodules.stamp $(RISCV)/install.stamp mkdir -p $(dir $@) - +flock -x $(dir $@)/chisel-lock $(MAKE) -C $(abspath $(TOP))/emulator CONFIG=$(patsubst stamps/%/emulator-debug.stamp,%,$@) RISCV=$(abspath $(RISCV)) CHISEL_VERSION=$(CHISEL_VERSION) debug + +flock -x $(dir $@)/chisel-lock $(MAKE) -C $(abspath $(TOP))/emulator CONFIG=$* RISCV=$(abspath $(RISCV)) CHISEL_VERSION=$(CHISEL_VERSION) debug date > $@ stamps/%/vsim-verilog.stamp: stamps/other-submodules.stamp $(RISCV)/install.stamp mkdir -p $(dir $@) - +flock -x $(dir $@)/chisel-lock $(MAKE) -C $(abspath $(TOP))/vsim CONFIG=$(patsubst stamps/%/vsim-verilog.stamp,%,$@) RISCV=$(abspath $(RISCV)) CHISEL_VERSION=$(CHISEL_VERSION) verilog + +flock -x $(dir $@)/chisel-lock $(MAKE) -C $(abspath $(TOP))/vsim CONFIG=$* RISCV=$(abspath $(RISCV)) CHISEL_VERSION=$(CHISEL_VERSION) verilog date > $@ stamps/%/vsim-ndebug.stamp: stamps/other-submodules.stamp $(RISCV)/install.stamp mkdir -p $(dir $@) - +flock -x $(dir $@)/chisel-lock $(MAKE) -C $(abspath $(TOP))/vsim CONFIG=$(patsubst stamps/%/vsim-ndebug.stamp,%,$@) RISCV=$(abspath $(RISCV)) CHISEL_VERSION=$(CHISEL_VERSION) + +flock -x $(dir $@)/chisel-lock $(MAKE) -C $(abspath $(TOP))/vsim CONFIG=$* RISCV=$(abspath $(RISCV)) CHISEL_VERSION=$(CHISEL_VERSION) date > $@ stamps/%/vsim-debug.stamp: stamps/other-submodules.stamp $(RISCV)/install.stamp mkdir -p $(dir $@) - +flock -x $(dir $@)/chisel-lock $(MAKE) -C $(abspath $(TOP))/vsim CONFIG=$(patsubst stamps/%/vsim-debug.stamp,%,$@) RISCV=$(abspath $(RISCV)) CHISEL_VERSION=$(CHISEL_VERSION) debug + +flock -x $(dir $@)/chisel-lock $(MAKE) -C $(abspath $(TOP))/vsim CONFIG=$* RISCV=$(abspath $(RISCV)) CHISEL_VERSION=$(CHISEL_VERSION) debug date > $@ stamps/%/fsim-verilog.stamp: stamps/other-submodules.stamp $(RISCV)/install.stamp mkdir -p $(dir $@) - +flock -x $(dir $@)/chisel-lock $(MAKE) -C $(abspath $(TOP))/fsim CONFIG=$(patsubst stamps/%/fsim-verilog.stamp,%,$@) RISCV=$(abspath $(RISCV)) CHISEL_VERSION=$(CHISEL_VERSION) verilog + +flock -x $(dir $@)/chisel-lock $(MAKE) -C $(abspath $(TOP))/fsim CONFIG=$* RISCV=$(abspath $(RISCV)) CHISEL_VERSION=$(CHISEL_VERSION) verilog date > $@ stamps/%/fsim-ndebug.stamp: stamps/other-submodules.stamp $(RISCV)/install.stamp mkdir -p $(dir $@) - +flock -x $(dir $@)/chisel-lock $(MAKE) -C $(abspath $(TOP))/fsim CONFIG=$(patsubst stamps/%/fsim-ndebug.stamp,%,$@) RISCV=$(abspath $(RISCV)) CHISEL_VERSION=$(CHISEL_VERSION) + +flock -x $(dir $@)/chisel-lock $(MAKE) -C $(abspath $(TOP))/fsim CONFIG=$* RISCV=$(abspath $(RISCV)) CHISEL_VERSION=$(CHISEL_VERSION) date > $@ stamps/%/fsim-debug.stamp: stamps/other-submodules.stamp $(RISCV)/install.stamp mkdir -p $(dir $@) - +flock -x $(dir $@)/chisel-lock $(MAKE) -C $(abspath $(TOP))/fsim CONFIG=$(patsubst stamps/%/fsim-debug.stamp,%,$@) RISCV=$(abspath $(RISCV)) CHISEL_VERSION=$(CHISEL_VERSION) debug + +flock -x $(dir $@)/chisel-lock $(MAKE) -C $(abspath $(TOP))/fsim CONFIG=$* RISCV=$(abspath $(RISCV)) CHISEL_VERSION=$(CHISEL_VERSION) debug date > $@ # Runs tests on one of the simulators stamps/%/emulator-asm-tests.stamp: stamps/other-submodules.stamp $(RISCV)/install.stamp mkdir -p $(dir $@) - $(MAKE) -C $(abspath $(TOP))/emulator CONFIG=$(patsubst stamps/%/emulator-asm-tests.stamp,%,$@) RISCV=$(abspath $(RISCV)) CHISEL_VERSION=$(CHISEL_VERSION) run-asm-tests-fast + $(MAKE) -C $(abspath $(TOP))/emulator CONFIG=$* RISCV=$(abspath $(RISCV)) CHISEL_VERSION=$(CHISEL_VERSION) run-asm-tests-fast date > $@ stamps/%/emulator-bmark-tests.stamp: stamps/other-submodules.stamp $(RISCV)/install.stamp mkdir -p $(dir $@) - $(MAKE) -C $(abspath $(TOP))/emulator CONFIG=$(patsubst stamps/%/emulator-bmark-tests.stamp,%,$@) RISCV=$(abspath $(RISCV)) CHISEL_VERSION=$(CHISEL_VERSION) run-bmark-tests-fast + $(MAKE) -C $(abspath $(TOP))/emulator CONFIG=$* RISCV=$(abspath $(RISCV)) CHISEL_VERSION=$(CHISEL_VERSION) run-bmark-tests-fast date > $@ stamps/%/vsim-asm-tests.stamp: stamps/other-submodules.stamp $(RISCV)/install.stamp mkdir -p $(dir $@) - $(MAKE) -C $(abspath $(TOP))/vsim CONFIG=$(patsubst stamps/%/vsim-asm-tests.stamp,%,$@) RISCV=$(abspath $(RISCV)) CHISEL_VERSION=$(CHISEL_VERSION) run-asm-tests-fast + $(MAKE) -C $(abspath $(TOP))/vsim CONFIG=$* RISCV=$(abspath $(RISCV)) CHISEL_VERSION=$(CHISEL_VERSION) run-asm-tests-fast date > $@ stamps/%/vsim-bmark-tests.stamp: stamps/other-submodules.stamp $(RISCV)/install.stamp mkdir -p $(dir $@) - $(MAKE) -C $(abspath $(TOP))/vsim CONFIG=$(patsubst stamps/%/vsim-bmark-tests.stamp,%,$@) RISCV=$(abspath $(RISCV)) CHISEL_VERSION=$(CHISEL_VERSION) run-bmark-tests-fast + $(MAKE) -C $(abspath $(TOP))/vsim CONFIG=$* RISCV=$(abspath $(RISCV)) CHISEL_VERSION=$(CHISEL_VERSION) run-bmark-tests-fast date > $@ stamps/%/fsim-asm-tests.stamp: stamps/other-submodules.stamp $(RISCV)/install.stamp mkdir -p $(dir $@) - $(MAKE) -C $(abspath $(TOP))/fsim CONFIG=$(patsubst stamps/%/fsim-asm-tests.stamp,%,$@) RISCV=$(abspath $(RISCV)) CHISEL_VERSION=$(CHISEL_VERSION) run-asm-tests-fast + $(MAKE) -C $(abspath $(TOP))/fsim CONFIG=$* RISCV=$(abspath $(RISCV)) CHISEL_VERSION=$(CHISEL_VERSION) run-asm-tests-fast date > $@ stamps/%/fsim-bmark-tests.stamp: stamps/other-submodules.stamp $(RISCV)/install.stamp mkdir -p $(dir $@) - $(MAKE) -C $(abspath $(TOP))/fsim CONFIG=$(patsubst stamps/%/fsim-bmark-tests.stamp,%,$@) RISCV=$(abspath $(RISCV)) CHISEL_VERSION=$(CHISEL_VERSION) run-bmark-tests-fast + $(MAKE) -C $(abspath $(TOP))/fsim CONFIG=$* RISCV=$(abspath $(RISCV)) CHISEL_VERSION=$(CHISEL_VERSION) run-bmark-tests-fast date > $@ # The torture tests run subtly differently on the different targets, so they # don't have pattern rules like everything else does. stamps/%/vsim-torture-$(TORTURE_CONFIG).stamp: stamps/%/vsim-debug.stamp stamps/%/vsim-ndebug.stamp mkdir -p $(dir $@) - $(MAKE) -C $(abspath $(TOP))/torture rnight RTL_CONFIG=$(patsubst stamps/%/vsim-debug.stamp,%,$<) RISCV=$(abspath $(RISCV)) PATH="$(abspath $(RISCV)/bin:$(PATH))" OPTIONS="-C $(abspath $(TOP)/torture/config/$(TORTURE_CONFIG).config) -p $(abspath $(TORTURE_SAVE_DIR)) -m 30 -t 10" + $(MAKE) -C $(abspath $(TOP))/torture rnight RTL_CONFIG=$* RISCV=$(abspath $(RISCV)) PATH="$(abspath $(RISCV)/bin:$(PATH))" OPTIONS="-C $(abspath $(TOP)/torture/config/$(TORTURE_CONFIG).config) -p $(abspath $(TORTURE_SAVE_DIR)) -m 30 -t 10" date > $@ stamps/%/emulator-torture-$(TORTURE_CONFIG).stamp: stamps/%/emulator-debug.stamp stamps/%/emulator-ndebug.stamp mkdir -p $(dir $@) - $(MAKE) -C $(abspath $(TOP))/torture cnight RTL_CONFIG=$(patsubst stamps/%/emulator-debug.stamp,%,$<) RISCV=$(abspath $(RISCV)) PATH="$(abspath $(RISCV)/bin:$(PATH))" OPTIONS="-C $(abspath $(TOP)/torture/config/$(TORTURE_CONFIG).config) -p $(abspath $(TORTURE_SAVE_DIR)) -m 30 -t 10" + $(MAKE) -C $(abspath $(TOP))/torture cnight RTL_CONFIG=$* RISCV=$(abspath $(RISCV)) PATH="$(abspath $(RISCV)/bin:$(PATH))" OPTIONS="-C $(abspath $(TOP)/torture/config/$(TORTURE_CONFIG).config) -p $(abspath $(TORTURE_SAVE_DIR)) -m 30 -t 10" date > $@ diff --git a/vsim/Makefrag-verilog b/vsim/Makefrag-verilog index fc9158d7..bb91682a 100644 --- a/vsim/Makefrag-verilog +++ b/vsim/Makefrag-verilog @@ -18,12 +18,12 @@ else $(generated_dir)/%.$(CONFIG).fir $(generated_dir)/%.$(CONFIG).d $(generated_dir)/%.prm: $(chisel_srcs) mkdir -p $(dir $@) - cd $(base_dir) && $(SBT) "run $(PROJECT) $(patsubst %.$(CONFIG).fir,%,$(patsubst %.d,%.fir,$(notdir $@))) $(CONFIG) $(CHISEL_ARGS) --configDump --noInlineMem" + cd $(base_dir) && $(SBT) "run $(PROJECT) $(notdir $*) $(CONFIG) $(CHISEL_ARGS) --configDump --noInlineMem" mv $(generated_dir)/$(MODEL).fir $(generated_dir)/$(MODEL).$(CONFIG).fir $(generated_dir)/%.v: $(generated_dir)/%.fir $(FIRRTL_JAR) mkdir -p $(dir $@) - $(FIRRTL) $(patsubst %,-i %,$(filter %.fir,$^)) -o $@ -X verilog + $(FIRRTL) -i $< -o $@ -X verilog endif