refactor NASTI to not use param; new AddrMap class
This commit is contained in:
Henry Cook
parent
a08872c0e9
commit
39a749843c
@ -6,21 +6,20 @@ import scala.math.max
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import scala.collection.mutable.ArraySeq
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import scala.collection.mutable.HashMap
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case object NastiBitWidths extends Field[NastiParameters]
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case object NastiAddrMap extends Field[AddrMap]
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case object MMIOBase extends Field[BigInt]
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case object NASTIDataBits extends Field[Int]
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case object NASTIAddrBits extends Field[Int]
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case object NASTIIdBits extends Field[Int]
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object bigIntPow2 {
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def apply(in: BigInt): Boolean = in > 0 && ((in & (in-1)) == 0)
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}
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case class NastiParameters(dataBits: Int, addrBits: Int, idBits: Int)
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trait NASTIParameters extends UsesParameters {
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val nastiXDataBits = params(NASTIDataBits)
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trait HasNastiParameters {
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implicit val p: Parameters
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val external = p(NastiBitWidths)
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val nastiXDataBits = external.dataBits
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val nastiWStrobeBits = nastiXDataBits / 8
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val nastiXAddrBits = params(NASTIAddrBits)
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val nastiWIdBits = params(NASTIIdBits)
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val nastiRIdBits = params(NASTIIdBits)
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val nastiXAddrBits = external.addrBits
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val nastiWIdBits = external.idBits
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val nastiRIdBits = external.idBits
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val nastiXIdBits = max(nastiWIdBits, nastiRIdBits)
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val nastiXUserBits = 1
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val nastiAWUserBits = nastiXUserBits
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@ -48,22 +47,16 @@ trait NASTIParameters extends UsesParameters {
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UInt(128) -> UInt(7)))
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}
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abstract class NASTIBundle extends Bundle with NASTIParameters
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abstract class NASTIModule extends Module with NASTIParameters
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trait NASTIChannel extends NASTIBundle
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trait NASTIMasterToSlaveChannel extends NASTIChannel
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trait NASTISlaveToMasterChannel extends NASTIChannel
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class NASTIIO extends Bundle {
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val aw = Decoupled(new NASTIWriteAddressChannel)
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val w = Decoupled(new NASTIWriteDataChannel)
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val b = Decoupled(new NASTIWriteResponseChannel).flip
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val ar = Decoupled(new NASTIReadAddressChannel)
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val r = Decoupled(new NASTIReadDataChannel).flip
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abstract class NastiModule extends Module with HasNastiParameters
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abstract class NastiBundle(implicit val p: Parameters) extends Bundle with HasNastiParameters {
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override def cloneType = this.getClass.getConstructors.head.newInstance(p).asInstanceOf[this.type]
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}
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trait HasNASTIMetadata extends NASTIBundle {
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abstract class NastiChannel(implicit p: Parameters) extends NastiBundle()(p)
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abstract class NastiMasterToSlaveChannel(implicit p: Parameters) extends NastiChannel()(p)
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abstract class NastiSlaveToMasterChannel(implicit p: Parameters) extends NastiChannel()(p)
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trait HasNastiMetadata extends HasNastiParameters {
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val addr = UInt(width = nastiXAddrBits)
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val len = UInt(width = nastiXLenBits)
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val size = UInt(width = nastiXSizeBits)
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@ -75,45 +68,56 @@ trait HasNASTIMetadata extends NASTIBundle {
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val region = UInt(width = nastiXRegionBits)
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}
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trait HasNASTIData extends NASTIBundle {
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trait HasNastiData extends HasNastiParameters {
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val data = UInt(width = nastiXDataBits)
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val last = Bool()
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}
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class NASTIAddressChannel extends NASTIMasterToSlaveChannel with HasNASTIMetadata
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class NastiIO(implicit p: Parameters) extends NastiBundle()(p) {
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val aw = Decoupled(new NastiWriteAddressChannel)
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val w = Decoupled(new NastiWriteDataChannel)
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val b = Decoupled(new NastiWriteResponseChannel).flip
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val ar = Decoupled(new NastiReadAddressChannel)
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val r = Decoupled(new NastiReadDataChannel).flip
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}
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class NASTIResponseChannel extends NASTISlaveToMasterChannel {
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class NastiAddressChannel(implicit p: Parameters) extends NastiMasterToSlaveChannel()(p)
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with HasNastiMetadata
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class NastiResponseChannel(implicit p: Parameters) extends NastiSlaveToMasterChannel()(p) {
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val resp = UInt(width = nastiXRespBits)
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}
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class NASTIWriteAddressChannel extends NASTIAddressChannel {
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class NastiWriteAddressChannel(implicit p: Parameters) extends NastiAddressChannel()(p) {
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val id = UInt(width = nastiWIdBits)
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val user = UInt(width = nastiAWUserBits)
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}
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class NASTIWriteDataChannel extends NASTIMasterToSlaveChannel with HasNASTIData {
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class NastiWriteDataChannel(implicit p: Parameters) extends NastiMasterToSlaveChannel()(p)
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with HasNastiData {
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val strb = UInt(width = nastiWStrobeBits)
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val user = UInt(width = nastiWUserBits)
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}
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class NASTIWriteResponseChannel extends NASTIResponseChannel {
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class NastiWriteResponseChannel(implicit p: Parameters) extends NastiResponseChannel()(p) {
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val id = UInt(width = nastiWIdBits)
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val user = UInt(width = nastiBUserBits)
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}
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class NASTIReadAddressChannel extends NASTIAddressChannel {
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class NastiReadAddressChannel(implicit p: Parameters) extends NastiAddressChannel()(p) {
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val id = UInt(width = nastiRIdBits)
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val user = UInt(width = nastiARUserBits)
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}
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class NASTIReadDataChannel extends NASTIResponseChannel with HasNASTIData {
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class NastiReadDataChannel(implicit p: Parameters) extends NastiResponseChannel()(p)
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with HasNastiData {
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val id = UInt(width = nastiRIdBits)
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val user = UInt(width = nastiRUserBits)
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}
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object NASTIWriteAddressChannel {
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def apply(id: UInt, addr: UInt, size: UInt, len: UInt = UInt(0)) = {
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val aw = Wire(new NASTIWriteAddressChannel)
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object NastiWriteAddressChannel {
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def apply(id: UInt, addr: UInt, size: UInt, len: UInt = UInt(0))(implicit p: Parameters) = {
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val aw = Wire(new NastiWriteAddressChannel)
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aw.id := id
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aw.addr := addr
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aw.len := len
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@ -129,9 +133,9 @@ object NASTIWriteAddressChannel {
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}
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}
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object NASTIReadAddressChannel {
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def apply(id: UInt, addr: UInt, size: UInt, len: UInt = UInt(0)) = {
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val ar = Wire(new NASTIReadAddressChannel)
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object NastiReadAddressChannel {
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def apply(id: UInt, addr: UInt, size: UInt, len: UInt = UInt(0))(implicit p: Parameters) = {
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val ar = Wire(new NastiReadAddressChannel)
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ar.id := id
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ar.addr := addr
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ar.len := len
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@ -147,22 +151,27 @@ object NASTIReadAddressChannel {
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}
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}
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object NASTIWriteDataChannel {
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private def strobeBits = new NASTIWriteDataChannel().nastiWStrobeBits
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def fullStrobe = Fill(strobeBits, UInt(1, 1))
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def apply(data: UInt, strb: UInt = fullStrobe, last: Bool = Bool(true)) = {
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val w = Wire(new NASTIWriteDataChannel)
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w.strb := strb
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object NastiWriteDataChannel {
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def apply(data: UInt, last: Bool = Bool(true))(implicit p: Parameters): NastiWriteDataChannel = {
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val w = Wire(new NastiWriteDataChannel)
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w.strb := Fill(w.nastiWStrobeBits, UInt(1, 1))
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w.data := data
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w.last := last
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w.user := UInt(0)
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w
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}
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def apply(data: UInt, strb: UInt, last: Bool)
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(implicit p: Parameters): NastiWriteDataChannel = {
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val w = apply(data, last)
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w.strb := strb
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w
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}
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}
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object NASTIReadDataChannel {
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def apply(id: UInt, data: UInt, last: Bool = Bool(true), resp: UInt = UInt(0)) = {
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val r = Wire(new NASTIReadDataChannel)
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object NastiReadDataChannel {
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def apply(id: UInt, data: UInt, last: Bool = Bool(true), resp: UInt = UInt(0))(
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implicit p: Parameters) = {
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val r = Wire(new NastiReadDataChannel)
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r.id := id
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r.data := data
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r.last := last
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@ -172,9 +181,9 @@ object NASTIReadDataChannel {
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}
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}
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object NASTIWriteResponseChannel {
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def apply(id: UInt, resp: UInt = UInt(0)) = {
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val b = Wire(new NASTIWriteResponseChannel)
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object NastiWriteResponseChannel {
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def apply(id: UInt, resp: UInt = UInt(0))(implicit p: Parameters) = {
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val b = Wire(new NastiWriteResponseChannel)
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b.id := id
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b.resp := resp
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b.user := UInt(0)
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@ -182,9 +191,10 @@ object NASTIWriteResponseChannel {
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}
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}
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class MemIONASTIIOConverter(cacheBlockOffsetBits: Int) extends MIFModule with NASTIParameters {
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class MemIONastiIOConverter(cacheBlockOffsetBits: Int)(implicit val p: Parameters) extends MIFModule
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with HasNastiParameters {
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val io = new Bundle {
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val nasti = (new NASTIIO).flip
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val nasti = (new NastiIO).flip
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val mem = new MemIO
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}
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@ -192,13 +202,13 @@ class MemIONASTIIOConverter(cacheBlockOffsetBits: Int) extends MIFModule with NA
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val (mif_cnt_out, mif_wrap_out) = Counter(io.mem.resp.fire(), mifDataBeats)
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assert(!io.nasti.aw.valid || io.nasti.aw.bits.size === UInt(log2Up(mifDataBits/8)),
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"NASTI data size does not match MemIO data size")
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"Nasti data size does not match MemIO data size")
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assert(!io.nasti.ar.valid || io.nasti.ar.bits.size === UInt(log2Up(mifDataBits/8)),
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"NASTI data size does not match MemIO data size")
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"Nasti data size does not match MemIO data size")
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assert(!io.nasti.aw.valid || io.nasti.aw.bits.len === UInt(mifDataBeats - 1),
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"NASTI length does not match number of MemIO beats")
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"Nasti length does not match number of MemIO beats")
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assert(!io.nasti.ar.valid || io.nasti.ar.bits.len === UInt(mifDataBeats - 1),
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"NASTI length does not match number of MemIO beats")
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"Nasti length does not match number of MemIO beats")
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// according to the spec, we can't send b until the last transfer on w
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val b_ok = Reg(init = Bool(true))
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@ -236,17 +246,17 @@ class MemIONASTIIOConverter(cacheBlockOffsetBits: Int) extends MIFModule with NA
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}
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/** Arbitrate among arbN masters requesting to a single slave */
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class NASTIArbiter(val arbN: Int) extends NASTIModule {
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class NastiArbiter(val arbN: Int)(implicit val p: Parameters) extends NastiModule {
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val io = new Bundle {
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val master = Vec(new NASTIIO, arbN).flip
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val slave = new NASTIIO
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val master = Vec(new NastiIO, arbN).flip
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val slave = new NastiIO
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}
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if (arbN > 1) {
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val arbIdBits = log2Up(arbN)
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val ar_arb = Module(new RRArbiter(new NASTIReadAddressChannel, arbN))
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val aw_arb = Module(new RRArbiter(new NASTIWriteAddressChannel, arbN))
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val ar_arb = Module(new RRArbiter(new NastiReadAddressChannel, arbN))
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val aw_arb = Module(new RRArbiter(new NastiWriteAddressChannel, arbN))
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val slave_r_arb_id = io.slave.r.bits.id(arbIdBits - 1, 0)
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val slave_b_arb_id = io.slave.b.bits.id(arbIdBits - 1, 0)
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@ -304,12 +314,12 @@ class NASTIArbiter(val arbN: Int) extends NASTIModule {
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} else { io.slave <> io.master.head }
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}
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/** Locking RR arbiter for NASTI read data channel
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/** Locking RR arbiter for Nasti read data channel
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* Arbiter locks until last message in channel is sent */
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class NASTIReadDataArbiter(arbN: Int) extends NASTIModule {
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class NastiReadDataArbiter(arbN: Int)(implicit val p: Parameters) extends NastiModule {
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val io = new Bundle {
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val in = Vec(Decoupled(new NASTIReadDataChannel), arbN).flip
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val out = Decoupled(new NASTIReadDataChannel)
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val in = Vec(Decoupled(new NastiReadDataChannel), arbN).flip
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val out = Decoupled(new NastiReadDataChannel)
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}
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def rotateLeft[T <: Data](norm: Vec[T], rot: UInt): Vec[T] = {
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@ -347,13 +357,13 @@ class NASTIReadDataArbiter(arbN: Int) extends NASTIModule {
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}
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/** A slave that send decode error for every request it receives */
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class NASTIErrorSlave extends NASTIModule {
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val io = (new NASTIIO).flip
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class NastiErrorSlave(implicit val p: Parameters) extends NastiModule {
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val io = (new NastiIO).flip
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when (io.ar.fire()) { printf("Invalid read address %x\n", io.ar.bits.addr) }
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when (io.aw.fire()) { printf("Invalid write address %x\n", io.aw.bits.addr) }
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val r_queue = Module(new Queue(new NASTIReadAddressChannel, 2))
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val r_queue = Module(new Queue(new NastiReadAddressChannel, 2))
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r_queue.io.enq <> io.ar
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val responding = Reg(init = Bool(false))
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@ -396,15 +406,15 @@ class NASTIErrorSlave extends NASTIModule {
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b_queue.io.deq.ready := io.b.ready && !draining
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}
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/** Take a single NASTI master and route its requests to various slaves
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/** Take a single Nasti master and route its requests to various slaves
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* @param addrmap a sequence of base address + memory size pairs,
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* on for each slave interface */
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class NASTIRouter(addrmap: Seq[(BigInt, BigInt)]) extends NASTIModule {
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class NastiRouter(addrmap: Seq[(BigInt, BigInt)])(implicit val p: Parameters) extends NastiModule {
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val nSlaves = addrmap.size
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val io = new Bundle {
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val master = (new NASTIIO).flip
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val slave = Vec(new NASTIIO, nSlaves)
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val master = (new NastiIO).flip
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val slave = Vec(new NastiIO, nSlaves)
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}
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var ar_ready = Bool(false)
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@ -446,7 +456,7 @@ class NASTIRouter(addrmap: Seq[(BigInt, BigInt)]) extends NASTIModule {
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w_ready = w_ready || (s.w.ready && chosen)
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}
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val err_slave = Module(new NASTIErrorSlave)
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val err_slave = Module(new NastiErrorSlave)
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err_slave.io.ar.valid := !r_valid_addr && io.master.ar.valid
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err_slave.io.ar.bits := io.master.ar.bits
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err_slave.io.aw.valid := !w_valid_addr && io.master.aw.valid
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@ -458,8 +468,8 @@ class NASTIRouter(addrmap: Seq[(BigInt, BigInt)]) extends NASTIModule {
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io.master.aw.ready := aw_ready || (!w_valid_addr && err_slave.io.aw.ready)
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io.master.w.ready := w_ready || err_slave.io.w.ready
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val b_arb = Module(new RRArbiter(new NASTIWriteResponseChannel, nSlaves + 1))
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val r_arb = Module(new NASTIReadDataArbiter(nSlaves + 1))
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val b_arb = Module(new RRArbiter(new NastiWriteResponseChannel, nSlaves + 1))
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val r_arb = Module(new NastiReadDataArbiter(nSlaves + 1))
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for (i <- 0 until nSlaves) {
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b_arb.io.in(i) <> io.slave(i).b
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@ -473,20 +483,20 @@ class NASTIRouter(addrmap: Seq[(BigInt, BigInt)]) extends NASTIModule {
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io.master.r <> r_arb.io.out
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}
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/** Crossbar between multiple NASTI masters and slaves
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* @param nMasters the number of NASTI masters
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* @param nSlaves the number of NASTI slaves
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/** Crossbar between multiple Nasti masters and slaves
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* @param nMasters the number of Nasti masters
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* @param nSlaves the number of Nasti slaves
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* @param addrmap a sequence of base - size pairs;
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* size of addrmap should be nSlaves */
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class NASTICrossbar(nMasters: Int, nSlaves: Int, addrmap: Seq[(BigInt, BigInt)])
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extends NASTIModule {
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class NastiCrossbar(nMasters: Int, nSlaves: Int, addrmap: Seq[(BigInt, BigInt)])
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(implicit val p: Parameters) extends NastiModule {
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val io = new Bundle {
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val masters = Vec(new NASTIIO, nMasters).flip
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val slaves = Vec(new NASTIIO, nSlaves)
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val masters = Vec(new NastiIO, nMasters).flip
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val slaves = Vec(new NastiIO, nSlaves)
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}
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val routers = Vec.fill(nMasters) { Module(new NASTIRouter(addrmap)).io }
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val arbiters = Vec.fill(nSlaves) { Module(new NASTIArbiter(nMasters)).io }
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val routers = Vec.fill(nMasters) { Module(new NastiRouter(addrmap)).io }
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val arbiters = Vec.fill(nSlaves) { Module(new NastiArbiter(nMasters)).io }
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for (i <- 0 until nMasters) {
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routers(i).master <> io.masters(i)
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@ -498,13 +508,7 @@ class NASTICrossbar(nMasters: Int, nSlaves: Int, addrmap: Seq[(BigInt, BigInt)])
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}
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}
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case object NASTINMasters extends Field[Int]
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case object NASTINSlaves extends Field[Int]
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object AddrMap {
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type AddrMapEntry = (String, Option[BigInt], MemRegion)
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type AddrMapSeq = Seq[AddrMapEntry]
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object AddrMapConsts {
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val R = 0x4
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val W = 0x2
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val X = 0x1
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@ -512,19 +516,6 @@ object AddrMap {
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val RX = R | X
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val RWX = R | W | X
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}
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import AddrMap._
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abstract class MemRegion { def size: BigInt }
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case class MemSize(size: BigInt, prot: Int) extends MemRegion
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case class MemSubmap(size: BigInt, entries: AddrMapSeq) extends MemRegion
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object Submap {
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def apply(size: BigInt, entries: AddrMapEntry*) =
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new MemSubmap(size, entries)
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}
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case class AddrHashMapEntry(port: Int, start: BigInt, size: BigInt, prot: Int)
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class AddrMapProt extends Bundle {
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val r = Bool()
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@ -532,14 +523,47 @@ class AddrMapProt extends Bundle {
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val x = Bool()
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}
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|
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class AddrHashMap(addrmap: AddrMapSeq) {
|
||||
abstract class MemRegion { def size: BigInt }
|
||||
|
||||
case class MemSize(size: BigInt, prot: Int) extends MemRegion
|
||||
|
||||
case class MemSubmap(size: BigInt, entries: AddrMap) extends MemRegion
|
||||
|
||||
//object Submap {
|
||||
// def apply(size: BigInt, entries: AddrMapEntry*) =
|
||||
// new MemSubmap(size, entries)
|
||||
//}
|
||||
|
||||
case class AddrMapEntry(name: String, start: Option[BigInt], region: MemRegion)
|
||||
|
||||
case class AddrHashMapEntry(port: Int, start: BigInt, size: BigInt, prot: Int)
|
||||
|
||||
class AddrMap(entries: Seq[AddrMapEntry]) extends scala.collection.IndexedSeq[AddrMapEntry] {
|
||||
|
||||
def apply(index: Int): AddrMapEntry = entries(index)
|
||||
|
||||
def length: Int = entries.size
|
||||
|
||||
def countSlaves: Int = {
|
||||
this map { entry: AddrMapEntry => entry.region match {
|
||||
case MemSize(_, _) => 1
|
||||
case MemSubmap(_, submap) => submap.countSlaves
|
||||
}} reduceLeft(_ + _)
|
||||
}
|
||||
}
|
||||
|
||||
object AddrMap {
|
||||
def apply(elems: AddrMapEntry*): AddrMap = new AddrMap(elems)
|
||||
}
|
||||
|
||||
class AddrHashMap(addrmap: AddrMap) {
|
||||
val mapping = new HashMap[String, AddrHashMapEntry]
|
||||
|
||||
private def genPairs(addrmap: AddrMapSeq): Seq[(String, AddrHashMapEntry)] = {
|
||||
private def genPairs(am: AddrMap): Seq[(String, AddrHashMapEntry)] = {
|
||||
var ind = 0
|
||||
var base = BigInt(0)
|
||||
var pairs = Seq[(String, AddrHashMapEntry)]()
|
||||
addrmap.foreach { case (name, startOpt, region) =>
|
||||
am.foreach { case AddrMapEntry(name, startOpt, region) =>
|
||||
region match {
|
||||
case MemSize(size, prot) => {
|
||||
if (!startOpt.isEmpty) base = startOpt.get
|
||||
@ -590,43 +614,35 @@ class AddrHashMap(addrmap: AddrMapSeq) {
|
||||
}
|
||||
}
|
||||
|
||||
case object NASTIAddrMap extends Field[AddrMapSeq]
|
||||
case object NASTIAddrHashMap extends Field[AddrHashMap]
|
||||
|
||||
class NASTIInterconnectIO(val nMasters: Int, val nSlaves: Int) extends Bundle {
|
||||
class NastiInterconnectIO(val nMasters: Int, val nSlaves: Int)
|
||||
(implicit p: Parameters) extends Bundle {
|
||||
/* This is a bit confusing. The interconnect is a slave to the masters and
|
||||
* a master to the slaves. Hence why the declarations seem to be backwards. */
|
||||
val masters = Vec(new NASTIIO, nMasters).flip
|
||||
val slaves = Vec(new NASTIIO, nSlaves)
|
||||
val masters = Vec(new NastiIO, nMasters).flip
|
||||
val slaves = Vec(new NastiIO, nSlaves)
|
||||
override def cloneType =
|
||||
new NASTIInterconnectIO(nMasters, nSlaves).asInstanceOf[this.type]
|
||||
new NastiInterconnectIO(nMasters, nSlaves).asInstanceOf[this.type]
|
||||
}
|
||||
|
||||
abstract class NASTIInterconnect extends NASTIModule {
|
||||
abstract class NastiInterconnect extends NastiModule {
|
||||
val nMasters: Int
|
||||
val nSlaves: Int
|
||||
|
||||
lazy val io = new NASTIInterconnectIO(nMasters, nSlaves)
|
||||
}
|
||||
|
||||
class NASTIRecursiveInterconnect(
|
||||
val nMasters: Int, val nSlaves: Int,
|
||||
addrmap: AddrMapSeq, base: BigInt = 0) extends NASTIInterconnect {
|
||||
|
||||
private def mapCountSlaves(addrmap: AddrMapSeq): Int = {
|
||||
addrmap.map {
|
||||
case (_, _, MemSize(_, _)) => 1
|
||||
case (_, _, MemSubmap(_, submap)) => mapCountSlaves(submap)
|
||||
}.reduceLeft(_ + _)
|
||||
lazy val io = new NastiInterconnectIO(nMasters, nSlaves)
|
||||
}
|
||||
|
||||
class NastiRecursiveInterconnect(
|
||||
val nMasters: Int,
|
||||
val nSlaves: Int,
|
||||
addrmap: AddrMap,
|
||||
base: BigInt = 0)
|
||||
(implicit val p: Parameters) extends NastiInterconnect {
|
||||
var lastEnd = base
|
||||
var slaveInd = 0
|
||||
val levelSize = addrmap.size
|
||||
|
||||
val realAddrMap = new ArraySeq[(BigInt, BigInt)](addrmap.size)
|
||||
|
||||
addrmap.zipWithIndex.foreach { case ((_, startOpt, region), i) =>
|
||||
addrmap.zipWithIndex.foreach { case (AddrMapEntry(_, startOpt, region), i) =>
|
||||
val start = startOpt.getOrElse(lastEnd)
|
||||
val size = region.size
|
||||
realAddrMap(i) = (start, size)
|
||||
@ -634,25 +650,24 @@ class NASTIRecursiveInterconnect(
|
||||
}
|
||||
|
||||
val flatSlaves = if (nMasters > 1) {
|
||||
val xbar = Module(new NASTICrossbar(nMasters, levelSize, realAddrMap))
|
||||
val xbar = Module(new NastiCrossbar(nMasters, levelSize, realAddrMap))
|
||||
xbar.io.masters <> io.masters
|
||||
xbar.io.slaves
|
||||
} else {
|
||||
val router = Module(new NASTIRouter(realAddrMap))
|
||||
val router = Module(new NastiRouter(realAddrMap))
|
||||
router.io.master <> io.masters.head
|
||||
router.io.slave
|
||||
}
|
||||
|
||||
addrmap.zip(realAddrMap).zipWithIndex.foreach {
|
||||
case (((_, _, region), (start, size)), i) => {
|
||||
region match {
|
||||
case ((entry, (start, size)), i) => {
|
||||
entry.region match {
|
||||
case MemSize(_, _) =>
|
||||
io.slaves(slaveInd) <> flatSlaves(i)
|
||||
slaveInd += 1
|
||||
case MemSubmap(_, submap) =>
|
||||
val subSlaves = mapCountSlaves(submap)
|
||||
val ic = Module(new NASTIRecursiveInterconnect(
|
||||
1, subSlaves, submap, start))
|
||||
val subSlaves = submap.countSlaves
|
||||
val ic = Module(new NastiRecursiveInterconnect(1, subSlaves, submap, start))
|
||||
ic.io.masters.head <> flatSlaves(i)
|
||||
io.slaves.drop(slaveInd).take(subSlaves).zip(ic.io.slaves).foreach {
|
||||
case (s, m) => s <> m
|
||||
@ -663,20 +678,15 @@ class NASTIRecursiveInterconnect(
|
||||
}
|
||||
}
|
||||
|
||||
class NASTITopInterconnect extends NASTIInterconnect {
|
||||
val nMasters = params(NASTINMasters)
|
||||
val nSlaves = params(NASTINSlaves)
|
||||
|
||||
bigIntPow2(params(MMIOBase))
|
||||
|
||||
val temp = Module(new NASTIRecursiveInterconnect(
|
||||
nMasters, nSlaves, params(NASTIAddrMap)))
|
||||
class NastiTopInterconnect(val nMasters: Int, val nSlaves: Int)
|
||||
(implicit val p: Parameters) extends NastiInterconnect {
|
||||
val temp = Module(new NastiRecursiveInterconnect(nMasters, nSlaves, p(NastiAddrMap)))
|
||||
|
||||
temp.io.masters.zip(io.masters).foreach { case (t, i) =>
|
||||
t.ar <> i.ar
|
||||
t.aw <> i.aw
|
||||
// this queue is necessary to break up the aw - w dependence
|
||||
// introduced by the TileLink -> NASTI converter
|
||||
// introduced by the TileLink -> Nasti converter
|
||||
t.w <> Queue(i.w)
|
||||
i.b <> t.b
|
||||
i.r <> t.r
|
||||
|
||||
@ -87,11 +87,11 @@ class SMIArbiter(val n: Int, val dataWidth: Int, val addrWidth: Int)
|
||||
io.out.resp.ready := io.in(choice).resp.ready
|
||||
}
|
||||
|
||||
class SMIIONASTIReadIOConverter(val dataWidth: Int, val addrWidth: Int)
|
||||
extends NASTIModule {
|
||||
class SMIIONastiReadIOConverter(val dataWidth: Int, val addrWidth: Int)
|
||||
(implicit val p: Parameters) extends NastiModule {
|
||||
val io = new Bundle {
|
||||
val ar = Decoupled(new NASTIReadAddressChannel).flip
|
||||
val r = Decoupled(new NASTIReadDataChannel)
|
||||
val ar = Decoupled(new NastiReadAddressChannel).flip
|
||||
val r = Decoupled(new NastiReadDataChannel)
|
||||
val smi = new SMIIO(dataWidth, addrWidth)
|
||||
}
|
||||
|
||||
@ -127,7 +127,7 @@ class SMIIONASTIReadIOConverter(val dataWidth: Int, val addrWidth: Int)
|
||||
io.smi.resp.ready := (state === s_read)
|
||||
|
||||
io.r.valid := (state === s_resp)
|
||||
io.r.bits := NASTIReadDataChannel(
|
||||
io.r.bits := NastiReadDataChannel(
|
||||
id = id,
|
||||
data = buffer.toBits,
|
||||
last = (nBeats === UInt(0)))
|
||||
@ -169,12 +169,12 @@ class SMIIONASTIReadIOConverter(val dataWidth: Int, val addrWidth: Int)
|
||||
}
|
||||
}
|
||||
|
||||
class SMIIONASTIWriteIOConverter(val dataWidth: Int, val addrWidth: Int)
|
||||
extends NASTIModule {
|
||||
class SMIIONastiWriteIOConverter(val dataWidth: Int, val addrWidth: Int)
|
||||
(implicit val p: Parameters) extends NastiModule {
|
||||
val io = new Bundle {
|
||||
val aw = Decoupled(new NASTIWriteAddressChannel).flip
|
||||
val w = Decoupled(new NASTIWriteDataChannel).flip
|
||||
val b = Decoupled(new NASTIWriteResponseChannel)
|
||||
val aw = Decoupled(new NastiWriteAddressChannel).flip
|
||||
val w = Decoupled(new NastiWriteDataChannel).flip
|
||||
val b = Decoupled(new NastiWriteResponseChannel)
|
||||
val smi = new SMIIO(dataWidth, addrWidth)
|
||||
}
|
||||
|
||||
@ -184,7 +184,7 @@ class SMIIONASTIWriteIOConverter(val dataWidth: Int, val addrWidth: Int)
|
||||
private val addrOffBits = addrWidth + byteOffBits
|
||||
|
||||
assert(!io.aw.valid || io.aw.bits.size >= UInt(byteOffBits),
|
||||
"NASTI size must be >= SMI size")
|
||||
"Nasti size must be >= SMI size")
|
||||
|
||||
val id = Reg(UInt(width = nastiWIdBits))
|
||||
val addr = Reg(UInt(width = addrWidth))
|
||||
@ -213,7 +213,7 @@ class SMIIONASTIWriteIOConverter(val dataWidth: Int, val addrWidth: Int)
|
||||
io.smi.req.bits.data := data(dataWidth - 1, 0)
|
||||
io.smi.resp.ready := (state === s_ack)
|
||||
io.b.valid := (state === s_resp)
|
||||
io.b.bits := NASTIWriteResponseChannel(id)
|
||||
io.b.bits := NastiWriteResponseChannel(id)
|
||||
|
||||
val jump = PriorityMux(strb(maxWordsPerBeat - 1, 1),
|
||||
(1 until maxWordsPerBeat).map(UInt(_)))
|
||||
@ -249,21 +249,21 @@ class SMIIONASTIWriteIOConverter(val dataWidth: Int, val addrWidth: Int)
|
||||
when (io.b.fire()) { state := s_idle }
|
||||
}
|
||||
|
||||
/** Convert NASTI protocol to SMI protocol */
|
||||
class SMIIONASTIIOConverter(val dataWidth: Int, val addrWidth: Int)
|
||||
extends NASTIModule {
|
||||
/** Convert Nasti protocol to SMI protocol */
|
||||
class SMIIONastiIOConverter(val dataWidth: Int, val addrWidth: Int)
|
||||
(implicit val p: Parameters) extends NastiModule {
|
||||
val io = new Bundle {
|
||||
val nasti = (new NASTIIO).flip
|
||||
val nasti = (new NastiIO).flip
|
||||
val smi = new SMIIO(dataWidth, addrWidth)
|
||||
}
|
||||
|
||||
require(isPow2(dataWidth), "SMI data width must be power of 2")
|
||||
|
||||
val reader = Module(new SMIIONASTIReadIOConverter(dataWidth, addrWidth))
|
||||
val reader = Module(new SMIIONastiReadIOConverter(dataWidth, addrWidth))
|
||||
reader.io.ar <> io.nasti.ar
|
||||
io.nasti.r <> reader.io.r
|
||||
|
||||
val writer = Module(new SMIIONASTIWriteIOConverter(dataWidth, addrWidth))
|
||||
val writer = Module(new SMIIONastiWriteIOConverter(dataWidth, addrWidth))
|
||||
writer.io.aw <> io.nasti.aw
|
||||
writer.io.w <> io.nasti.w
|
||||
io.nasti.b <> writer.io.b
|
||||
|
||||
7
junctions/src/main/scala/util.scala
Normal file
7
junctions/src/main/scala/util.scala
Normal file
@ -0,0 +1,7 @@
|
||||
/// See LICENSE for license details.
|
||||
package junctions
|
||||
import Chisel._
|
||||
|
||||
object bigIntPow2 {
|
||||
def apply(in: BigInt): Boolean = in > 0 && ((in & (in-1)) == 0)
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user