AXI4: add an optional user bundle field
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@ -70,9 +70,13 @@ case class AXI4MasterParameters(
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}
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case class AXI4MasterPortParameters(
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masters: Seq[AXI4MasterParameters])
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masters: Seq[AXI4MasterParameters],
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userBits: Int = 0,
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maxFlight: Int = 0) // at most X transactions per ID (0 = unlimited)
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{
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val endId = masters.map(_.id.end).max
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require (userBits >= 0)
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require (maxFlight >= 0)
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// Require disjoint ranges for ids
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masters.combinations(2).foreach { case Seq(x,y) => require (!x.id.overlaps(y.id), s"$x and $y overlap") }
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@ -81,7 +85,8 @@ case class AXI4MasterPortParameters(
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case class AXI4BundleParameters(
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addrBits: Int,
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dataBits: Int,
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idBits: Int)
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idBits: Int,
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userBits: Int)
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{
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require (dataBits >= 8, s"AXI4 data bits must be >= 8 (got $dataBits)")
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require (addrBits >= 1, s"AXI4 addr bits must be >= 1 (got $addrBits)")
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@ -102,19 +107,21 @@ case class AXI4BundleParameters(
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AXI4BundleParameters(
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max(addrBits, x.addrBits),
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max(dataBits, x.dataBits),
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max(idBits, x.idBits))
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max(idBits, x.idBits),
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max(userBits, x.userBits))
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}
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object AXI4BundleParameters
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{
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val emptyBundleParams = AXI4BundleParameters(addrBits=1, dataBits=8, idBits=1)
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val emptyBundleParams = AXI4BundleParameters(addrBits=1, dataBits=8, idBits=1, userBits=0)
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def union(x: Seq[AXI4BundleParameters]) = x.foldLeft(emptyBundleParams)((x,y) => x.union(y))
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def apply(master: AXI4MasterPortParameters, slave: AXI4SlavePortParameters) =
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new AXI4BundleParameters(
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addrBits = log2Up(slave.maxAddress+1),
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dataBits = slave.beatBytes * 8,
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idBits = log2Up(master.endId))
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idBits = log2Up(master.endId),
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userBits = master.userBits)
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}
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case class AXI4EdgeParameters(
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