From 395e4e3dd6a82cfae9dacaf971d667ffca71284b Mon Sep 17 00:00:00 2001 From: Yunsup Lee Date: Sun, 18 Nov 2012 03:11:06 -0800 Subject: [PATCH] andrew'x fix for D$ corner case in writeback->abort->probe --- rocket/src/main/scala/nbdcache.scala | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/rocket/src/main/scala/nbdcache.scala b/rocket/src/main/scala/nbdcache.scala index 3a3ba883..f418682d 100644 --- a/rocket/src/main/scala/nbdcache.scala +++ b/rocket/src/main/scala/nbdcache.scala @@ -190,6 +190,7 @@ class MSHR(id: Int)(implicit conf: DCacheConfig) extends Component { val finish_q = (new Queue(2 /* wb + refill */)) { new TransactionFinish } finish_q.io.enq.valid := wb_done || refill_done finish_q.io.enq.bits.global_xact_id := io.mem_rep.bits.global_xact_id + io.wb_req.valid := Bool(false) when (state === s_drain_rpq && !rpq.io.deq.valid && !finish_q.io.deq.valid) { state := s_invalid @@ -217,8 +218,11 @@ class MSHR(id: Int)(implicit conf: DCacheConfig) extends Component { when (abort) { state := s_wb_req } } when (state === s_wb_req) { - when (io.probe_writeback.valid && io.probe_writeback.bits && idx_match) { state := s_refill_req } - .elsewhen (io.wb_req.ready) { state := s_wb_resp } + io.wb_req.valid := Bool(true) + when (io.probe_writeback.valid && idx_match) { + io.wb_req.valid := Bool(false) + when (io.probe_writeback.bits) { state := s_refill_req } + }.elsewhen (io.wb_req.ready) { state := s_wb_resp } } when (io.req_sec_val && io.req_sec_rdy) { // s_wb_req, s_wb_resp, s_refill_req @@ -246,7 +250,6 @@ class MSHR(id: Int)(implicit conf: DCacheConfig) extends Component { io.meta_req.bits.data.tag := io.tag io.meta_req.bits.way_en := req.way_en - io.wb_req.valid := (state === s_wb_req) && !(io.probe_writeback.valid && idx_match) io.wb_req.bits.tag := req.old_tag io.wb_req.bits.idx := req_idx io.wb_req.bits.way_en := req.way_en