Force each TLB entry into its own clock-gate group
This ameliorates a PMP critical path. I can't figure out how to do this without asUInt/asTypeOf.
This commit is contained in:
Andrew Waterman
parent
8d7f1d777e
commit
3951e57789
@ -43,19 +43,32 @@ class TLBResp(implicit p: Parameters) extends CoreBundle()(p) {
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val cacheable = Bool(OUTPUT)
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}
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class TLB(lgMaxSize: Int, entries: Int)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()(p) {
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class TLB(lgMaxSize: Int, nEntries: Int)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()(p) {
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val io = new Bundle {
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val req = Decoupled(new TLBReq(lgMaxSize)).flip
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val resp = new TLBResp
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val ptw = new TLBPTWIO
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}
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val totalEntries = entries + 1
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val normalEntries = entries
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val specialEntry = entries
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class Entry extends Bundle {
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val ppn = UInt(width = ppnBits)
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val tag = UInt(width = asIdBits + vpnBits)
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val level = UInt(width = log2Ceil(pgLevels))
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val u = Bool()
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val g = Bool()
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val sw = Bool()
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val sx = Bool()
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val sr = Bool()
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val xr = Bool()
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val cacheable = Bool()
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}
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val totalEntries = nEntries + 1
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val normalEntries = nEntries
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val specialEntry = nEntries
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val valid = Reg(init = UInt(0, totalEntries))
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val ppns = Reg(Vec(totalEntries, UInt(width = ppnBits)))
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val tags = Reg(Vec(totalEntries, UInt(width = asIdBits + vpnBits)))
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val levels = Reg(Vec(totalEntries, UInt(width = log2Ceil(pgLevels))))
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val reg_entries = Reg(Vec(totalEntries, UInt(width = new Entry().getWidth)))
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val entries = reg_entries.map(_.asTypeOf(new Entry))
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val s_ready :: s_request :: s_wait :: s_wait_invalidate :: Nil = Enum(UInt(), 4)
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val state = Reg(init=s_ready)
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@ -74,7 +87,7 @@ class TLB(lgMaxSize: Int, entries: Int)(implicit edge: TLEdgeOut, p: Parameters)
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val do_refill = Bool(usingVM) && io.ptw.resp.valid
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val invalidate_refill = state.isOneOf(s_request /* don't care */, s_wait_invalidate)
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val mpu_ppn = Mux(do_refill, refill_ppn,
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Mux(vm_enabled, ppns.last, vpn(ppnBits-1, 0)))
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Mux(vm_enabled, entries.last.ppn, vpn(ppnBits-1, 0)))
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val mpu_physaddr = Cat(mpu_ppn, io.req.bits.vaddr(pgIdxBits-1, 0))
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val pmp = Module(new PMPChecker(lgMaxSize))
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pmp.io.addr := mpu_physaddr
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@ -95,13 +108,13 @@ class TLB(lgMaxSize: Int, entries: Int)(implicit edge: TLEdgeOut, p: Parameters)
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var tagMatch = valid(i)
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for (j <- 0 until pgLevels) {
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val base = vpnBits - (j + 1) * pgLevelBits
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tagMatch = tagMatch && (levels(i) < j || tags(i)(base + pgLevelBits - 1, base) === vpn(base + pgLevelBits - 1, base))
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tagMatch = tagMatch && (entries(i).level < j || entries(i).tag(base + pgLevelBits - 1, base) === vpn(base + pgLevelBits - 1, base))
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}
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tagMatch
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}} :+ !vm_enabled
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val hits = hitsVec.asUInt
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val level = Mux1H(hitsVec.init, levels)
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val partialPPN = Mux1H(hitsVec.init, ppns)
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val level = Mux1H(hitsVec.init, entries.map(_.level))
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val partialPPN = Mux1H(hitsVec.init, entries.map(_.ppn))
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val ppn = {
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var ppn = Mux(vm_enabled, partialPPN, vpn)(pgLevelBits*pgLevels - 1, pgLevelBits*(pgLevels - 1))
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for (i <- 1 until pgLevels)
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@ -110,39 +123,40 @@ class TLB(lgMaxSize: Int, entries: Int)(implicit edge: TLEdgeOut, p: Parameters)
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}
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// permission bit arrays
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val u_array = Reg(UInt(width = totalEntries)) // user permission
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val g_array = Reg(UInt(width = totalEntries)) // global mapping
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val sw_array = Reg(UInt(width = totalEntries)) // write permission
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val sx_array = Reg(UInt(width = totalEntries)) // execute permission
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val sr_array = Reg(UInt(width = totalEntries)) // read permission
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val xr_array = Reg(UInt(width = totalEntries)) // read permission to executable page
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val cash_array = Reg(UInt(width = normalEntries)) // cacheable
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val u_array = Reg(Vec(totalEntries, Bool())) // user permission
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val g_array = Reg(Vec(totalEntries, Bool())) // global mapping
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val sw_array = Reg(Vec(totalEntries, Bool())) // write permission
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val sx_array = Reg(Vec(totalEntries, Bool())) // execute permission
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val sr_array = Reg(Vec(totalEntries, Bool())) // read permission
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val xr_array = Reg(Vec(totalEntries, Bool())) // read permission to executable page
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val cash_array = Reg(Vec(normalEntries, Bool())) // cacheable
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when (do_refill && !invalidate_refill) {
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val waddr = Mux(isSpecial, specialEntry.U, r_refill_waddr)
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val pte = io.ptw.resp.bits.pte
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ppns(waddr) := pte.ppn
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tags(waddr) := r_refill_tag
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levels(waddr) := io.ptw.resp.bits.level
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val newEntry = Wire(new Entry)
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newEntry.ppn := pte.ppn
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newEntry.tag := r_refill_tag
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newEntry.level := io.ptw.resp.bits.level
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newEntry.u := pte.u
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newEntry.g := pte.g
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newEntry.sw := pte.sw() && (isSpecial || prot_w)
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newEntry.sx := pte.sx() && (isSpecial || prot_x)
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newEntry.sr := pte.sr() && (isSpecial || prot_r)
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newEntry.xr := pte.sx() && (isSpecial || prot_r)
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newEntry.cacheable := isSpecial || cacheable
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val mask = UIntToOH(waddr)
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valid := valid | mask
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u_array := Mux(pte.u, u_array | mask, u_array & ~mask)
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g_array := Mux(pte.g, g_array | mask, g_array & ~mask)
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sw_array := Mux(pte.sw() && (isSpecial || prot_w), sw_array | mask, sw_array & ~mask)
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sx_array := Mux(pte.sx() && (isSpecial || prot_x), sx_array | mask, sx_array & ~mask)
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sr_array := Mux(pte.sr() && (isSpecial || prot_r), sr_array | mask, sr_array & ~mask)
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xr_array := Mux(pte.sx() && (isSpecial || prot_r), xr_array | mask, xr_array & ~mask)
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cash_array := Mux(cacheable, cash_array | mask, cash_array & ~mask)
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valid := valid | UIntToOH(waddr)
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reg_entries(waddr) := newEntry.asUInt
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}
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val plru = new PseudoLRU(normalEntries)
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val repl_waddr = Mux(!valid(normalEntries-1, 0).andR, PriorityEncoder(~valid(normalEntries-1, 0)), plru.replace)
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val priv_ok = Mux(priv_s, ~Mux(io.ptw.status.sum, UInt(0), u_array), u_array)
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val w_array = Cat(prot_w, priv_ok & ~(~prot_w << specialEntry) & sw_array)
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val x_array = Cat(prot_x, priv_ok & ~(~prot_x << specialEntry) & sx_array)
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val r_array = Cat(prot_r, priv_ok & ~(~prot_r << specialEntry) & (sr_array | Mux(io.ptw.status.mxr, xr_array, UInt(0))))
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val c_array = Cat(cacheable, cacheable, cash_array)
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val priv_ok = Mux(priv_s, ~Mux(io.ptw.status.sum, UInt(0), entries.map(_.u).asUInt), entries.map(_.u).asUInt)
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val w_array = Cat(prot_w, priv_ok & ~(~prot_w << specialEntry) & entries.map(_.sw).asUInt)
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val x_array = Cat(prot_x, priv_ok & ~(~prot_x << specialEntry) & entries.map(_.sx).asUInt)
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val r_array = Cat(prot_r, priv_ok & ~(~prot_r << specialEntry) & (entries.map(_.sr).asUInt | Mux(io.ptw.status.mxr, entries.map(_.xr).asUInt, UInt(0))))
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val c_array = Cat(cacheable, ~(~cacheable << specialEntry) & entries.map(_.cacheable).asUInt)
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val bad_va =
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if (vpnBits == vpnBitsExtended) Bool(false)
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@ -194,7 +208,7 @@ class TLB(lgMaxSize: Int, entries: Int)(implicit edge: TLEdgeOut, p: Parameters)
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when (sfence) {
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valid := Mux(io.req.bits.sfence.bits.rs1, valid & ~hits(totalEntries-1, 0),
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Mux(io.req.bits.sfence.bits.rs2, valid & g_array, 0))
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Mux(io.req.bits.sfence.bits.rs2, valid & g_array.asUInt, 0))
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}
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when (multipleHits) {
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valid := 0
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