riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

coreplex: assume L1 runs no slower than L2

Browse Source
This commit is contained in:
Wesley W. Terpstra 2017-02-17 15:15:41 +01:00
parent 5045696f92
commit 3931b0faff
2 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/main/scala/coreplex/RocketTiles.scala
View File

@ -73,7 +73,7 @@ trait HasRocketTiles extends CoreplexRISCVPlatform {
}
case Rational => {
val wrapper = LazyModule(new RationalRocketTile(c)(pWithExtra))
val sink = LazyModule(new TLRationalCrossingSink)
val sink = LazyModule(new TLRationalCrossingSink(util.FastToSlow))
val source = LazyModule(new TLRationalCrossingSource)
sink.node :=* wrapper.masterNode
l1tol2.node :=* sink.node

2
src/main/scala/rocket/Tile.scala
View File

@ -103,7 +103,7 @@ class RationalRocketTile(rtp: RocketTileParams)(implicit p: Parameters) extends
masterNode :=* source.node
val slaveNode = TLRationalInputNode()
val sink = LazyModule(new TLRationalCrossingSink)
val sink = LazyModule(new TLRationalCrossingSink(util.SlowToFast))
rocket.slaveNode :*= sink.node
sink.node :*= slaveNode