riscv/rocket-chip
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coreplex: assume L1 runs no slower than L2

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This commit is contained in:
Wesley W. Terpstra
2017-02-17 15:15:41 +01:00
parent 5045696f92
commit 3931b0faff
2 changed files with 2 additions and 2 deletions
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src/main/scala/coreplex/RocketTiles.scala
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@ -73,7 +73,7 @@ trait HasRocketTiles extends CoreplexRISCVPlatform {
}
case Rational => {
val wrapper = LazyModule(new RationalRocketTile(c)(pWithExtra))
val sink = LazyModule(new TLRationalCrossingSink)
val sink = LazyModule(new TLRationalCrossingSink(util.FastToSlow))
val source = LazyModule(new TLRationalCrossingSource)
sink.node :=* wrapper.masterNode
l1tol2.node :=* sink.node