From 391be8d7409d12dc247c4928aba441827b7482f8 Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Thu, 22 Sep 2016 15:36:13 -0700 Subject: [PATCH] tilelink2 RegisterRouter: minLatency is never more than 1 --- src/main/scala/uncore/tilelink2/RegisterRouter.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/scala/uncore/tilelink2/RegisterRouter.scala b/src/main/scala/uncore/tilelink2/RegisterRouter.scala index 44802259..f7b77685 100644 --- a/src/main/scala/uncore/tilelink2/RegisterRouter.scala +++ b/src/main/scala/uncore/tilelink2/RegisterRouter.scala @@ -3,7 +3,7 @@ package uncore.tilelink2 import Chisel._ -import scala.math.max +import scala.math.{min,max} class TLRegisterNode(address: AddressSet, concurrency: Int = 0, beatBytes: Int = 4, undefZero: Boolean = true) extends TLManagerNode(beatBytes, TLManagerParameters( @@ -12,7 +12,7 @@ class TLRegisterNode(address: AddressSet, concurrency: Int = 0, beatBytes: Int = supportsPutPartial = TransferSizes(1, beatBytes), supportsPutFull = TransferSizes(1, beatBytes), fifoId = Some(0)), // requests are handled in order - minLatency = max(concurrency, 1)) // the Queue adds at least one cycle + minLatency = min(concurrency, 1)) // the Queue adds at least one cycle { require (address.contiguous)