parameterized multiplier unrolling
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733fc8e65e
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@ -23,8 +23,14 @@ class ioMultiplier(width: Int) extends Bundle {
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class rocketMultiplier extends Component {
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class rocketMultiplier extends Component {
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val io = new ioMultiplier(64);
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val io = new ioMultiplier(64);
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// width must be even (booth).
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// we need an extra bit to handle signed vs. unsigned,
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// so we need to add a second to keep width even.
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val width = 64 + 2
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val width = 64 + 2
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val cycles = width/2
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// unroll must divide width/2
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val unroll = 3
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val cycles = width/unroll/2
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val r_val = Reg(resetVal = Bool(false));
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val r_val = Reg(resetVal = Bool(false));
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val r_dw = Reg { UFix() }
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val r_dw = Reg { UFix() }
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@ -62,17 +68,25 @@ class rocketMultiplier extends Component {
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val lhs_sext = Cat(r_lhs(width-2), r_lhs(width-2), r_lhs).toUFix
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val lhs_sext = Cat(r_lhs(width-2), r_lhs(width-2), r_lhs).toUFix
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val lhs_twice = Cat(r_lhs(width-2), r_lhs, Bits(0,1)).toUFix
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val lhs_twice = Cat(r_lhs(width-2), r_lhs, Bits(0,1)).toUFix
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val addend = Mux(r_prod(0) != r_lsb, lhs_sext,
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var prod = r_prod
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Mux(r_prod(0) != r_prod(1), lhs_twice,
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var lsb = r_lsb
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UFix(0)));
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val sub = r_prod(1)
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for (i <- 0 until unroll) {
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val adder_lhs = Cat(r_prod(width*2-1), r_prod(width*2-1,width)).toUFix
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val addend = Mux(prod(0) != lsb, lhs_sext,
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val adder_rhs = Mux(sub, ~addend, addend)
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Mux(prod(0) != prod(1), lhs_twice,
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val adder_out = (adder_lhs + adder_rhs + sub.toUFix)(width,0)
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UFix(0)));
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val sub = prod(1)
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val adder_lhs = Cat(prod(width*2-1), prod(width*2-1,width)).toUFix
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val adder_rhs = Mux(sub, ~addend, addend)
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val adder_out = (adder_lhs + adder_rhs + sub.toUFix)(width,0)
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lsb = prod(1)
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prod = Cat(adder_out(width), adder_out, prod(width-1,2))
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}
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when (r_val && (r_cnt != UFix(cycles))) {
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when (r_val && (r_cnt != UFix(cycles))) {
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r_lsb <== r_prod(1)
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r_lsb <== lsb
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r_prod <== Cat(adder_out(width), adder_out, r_prod(width-1,2))
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r_prod <== prod
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r_cnt <== r_cnt + UFix(1)
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r_cnt <== r_cnt + UFix(1)
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}
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}
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