riscv/rocket-chip
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BankedL2: move TLFilter BEFORE coherence manager

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This lets smart caches exclude the sets that are filtered.
This commit is contained in:
Wesley W. Terpstra 2017-01-21 13:23:07 -08:00
parent dcadd5a006
commit 38c9ddffcc
1 changed files with 2 additions and 2 deletions
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src/main/scala/coreplex/CoreplexNetwork.scala
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@ -77,8 +77,8 @@ trait BankedL2CoherenceManagers extends CoreplexNetwork {
val mask = ~BigInt((l2Config.nBanksPerChannel-1) * l1tol2_lineBytes) val mask = ~BigInt((l2Config.nBanksPerChannel-1) * l1tol2_lineBytes)
for (i <- 0 until l2Config.nBanksPerChannel) { for (i <- 0 until l2Config.nBanksPerChannel) {
val (in, out) = l2Config.coherenceManager(p) val (in, out) = l2Config.coherenceManager(p)
in := TLFilter(AddressSet(i * l1tol2_lineBytes, mask))(l1tol2.node) in := l1tol2.node
bankBar.node := out bankBar.node := TLFilter(AddressSet(i * l1tol2_lineBytes, mask))(out)
} }
} }
} }