riscv/rocket-chip
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cleanups supporting uncore hierarchy

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This commit is contained in:
Henry Cook 2014-01-21 12:37:47 -08:00
parent e9d3a650a4
commit 382fa0ef27
6 changed files with 79 additions and 76 deletions
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2
riscv-tests

@ -1 +1 @@
Subproject commit 7bf1cfb4bc537f8854b298cf4565974dcc2b85b9 Subproject commit 6ff9837501d34c1c8f87ded1fb05fe95987dba2d

2
rocket

@ -1 +1 @@
Subproject commit 94ebacced6aa2bf1e7e0761a0fb0e547d172ee12 Subproject commit 2053e9f752962e47e9a38ddd540f986a2fe32038

16
src/main/scala/RocketChip.scala
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@ -83,7 +83,7 @@ class ReferenceChipBackend extends VerilogBackend
transforms += ((c: Module) => collectNodesIntoComp(initializeDFS)) transforms += ((c: Module) => collectNodesIntoComp(initializeDFS))
} }
class OuterMemorySystem(htif_width: Int, clientEndpoints: Seq[ClientCoherenceAgent])(implicit conf: UncoreConfiguration) extends Module class OuterMemorySystem(htif_width: Int)(implicit conf: UncoreConfiguration) extends Module
{ {
implicit val (tl, ln, l2) = (conf.tl, conf.tl.ln, conf.l2) implicit val (tl, ln, l2) = (conf.tl, conf.tl.ln, conf.l2)
val io = new Bundle { val io = new Bundle {
@ -101,10 +101,10 @@ class OuterMemorySystem(htif_width: Int, clientEndpoints: Seq[ClientCoherenceAge
//val llc = Module(new DRAMSideLLCNull(NL2_REL_XACTS+NL2_ACQ_XACTS, REFILL_CYCLES)) //val llc = Module(new DRAMSideLLCNull(NL2_REL_XACTS+NL2_ACQ_XACTS, REFILL_CYCLES))
val mem_serdes = Module(new MemSerdes(htif_width)) val mem_serdes = Module(new MemSerdes(htif_width))
require(clientEndpoints.length == ln.nClients)
val masterEndpoints = (0 until ln.nMasters).map(i => Module(new L2CoherenceAgent(i))) val masterEndpoints = (0 until ln.nMasters).map(i => Module(new L2CoherenceAgent(i)))
val net = Module(new ReferenceChipCrossbarNetwork(masterEndpoints++clientEndpoints)) val net = Module(new ReferenceChipCrossbarNetwork)
net.io zip (masterEndpoints.map(_.io.client) ++ io.tiles :+ io.htif) map { case (net, end) => net <> end } net.io.clients zip (io.tiles :+ io.htif) map { case (net, end) => net <> end }
net.io.masters zip (masterEndpoints.map(_.io.client)) map { case (net, end) => net <> end }
masterEndpoints.map{ _.io.incoherent zip io.incoherent map { case (m, c) => m := c } } masterEndpoints.map{ _.io.incoherent zip io.incoherent map { case (m, c) => m := c } }
val conv = Module(new MemIOUncachedTileLinkIOConverter(2)) val conv = Module(new MemIOUncachedTileLinkIOConverter(2))
@ -145,7 +145,7 @@ class OuterMemorySystem(htif_width: Int, clientEndpoints: Seq[ClientCoherenceAge
case class UncoreConfiguration(l2: L2CoherenceAgentConfiguration, tl: TileLinkConfiguration, nTiles: Int, nBanks: Int, bankIdLsb: Int, nSCR: Int) case class UncoreConfiguration(l2: L2CoherenceAgentConfiguration, tl: TileLinkConfiguration, nTiles: Int, nBanks: Int, bankIdLsb: Int, nSCR: Int)
class Uncore(htif_width: Int, tileList: Seq[ClientCoherenceAgent])(implicit conf: UncoreConfiguration) extends Module class Uncore(htif_width: Int)(implicit conf: UncoreConfiguration) extends Module
{ {
implicit val tl = conf.tl implicit val tl = conf.tl
val io = new Bundle { val io = new Bundle {
@ -158,7 +158,7 @@ class Uncore(htif_width: Int, tileList: Seq[ClientCoherenceAgent])(implicit conf
val mem_backup_en = Bool(INPUT) val mem_backup_en = Bool(INPUT)
} }
val htif = Module(new HTIF(htif_width, CSRs.reset, conf.nSCR)) val htif = Module(new HTIF(htif_width, CSRs.reset, conf.nSCR))
val outmemsys = Module(new OuterMemorySystem(htif_width, tileList :+ htif)) val outmemsys = Module(new OuterMemorySystem(htif_width))
val incoherentWithHtif = (io.incoherent :+ Bool(true).asInput) val incoherentWithHtif = (io.incoherent :+ Bool(true).asInput)
outmemsys.io.incoherent := incoherentWithHtif outmemsys.io.incoherent := incoherentWithHtif
htif.io.cpu <> io.htif htif.io.cpu <> io.htif
@ -246,7 +246,7 @@ class Top extends Module {
else new MICoherence else new MICoherence
} }
implicit val ln = LogicalNetworkConfiguration(NTILES+NBANKS+1, log2Up(NTILES)+1, NBANKS, NTILES+1) implicit val ln = LogicalNetworkConfiguration(log2Up(NTILES)+1, NBANKS, NTILES+1)
implicit val tl = TileLinkConfiguration(co, ln, log2Up(NL2_REL_XACTS+NL2_ACQ_XACTS), 2*log2Up(NMSHRS*NTILES+1), MEM_DATA_BITS) implicit val tl = TileLinkConfiguration(co, ln, log2Up(NL2_REL_XACTS+NL2_ACQ_XACTS), 2*log2Up(NMSHRS*NTILES+1), MEM_DATA_BITS)
implicit val l2 = L2CoherenceAgentConfiguration(tl, NL2_REL_XACTS, NL2_ACQ_XACTS) implicit val l2 = L2CoherenceAgentConfiguration(tl, NL2_REL_XACTS, NL2_ACQ_XACTS)
implicit val uc = UncoreConfiguration(l2, tl, NTILES, NBANKS, bankIdLsb = 5, nSCR = 64) implicit val uc = UncoreConfiguration(l2, tl, NTILES, NBANKS, bankIdLsb = 5, nSCR = 64)
@ -261,7 +261,7 @@ class Top extends Module {
val resetSigs = Vec.fill(uc.nTiles){Bool()} val resetSigs = Vec.fill(uc.nTiles){Bool()}
val tileList = (0 until uc.nTiles).map(r => Module(new Tile(resetSignal = resetSigs(r))(rc))) val tileList = (0 until uc.nTiles).map(r => Module(new Tile(resetSignal = resetSigs(r))(rc)))
val uncore = Module(new Uncore(HTIF_WIDTH, tileList)) val uncore = Module(new Uncore(HTIF_WIDTH))
for (i <- 0 until uc.nTiles) { for (i <- 0 until uc.nTiles) {
val hl = uncore.io.htif(i) val hl = uncore.io.htif(i)

16
src/main/scala/fpga.scala
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@ -5,7 +5,7 @@ import Node._
import uncore._ import uncore._
import rocket._ import rocket._
class FPGAOuterMemorySystem(htif_width: Int, clientEndpoints: Seq[ClientCoherenceAgent])(implicit conf: UncoreConfiguration) extends Module class FPGAOuterMemorySystem(htif_width: Int)(implicit conf: UncoreConfiguration) extends Module
{ {
implicit val (tl, ln, l2) = (conf.tl, conf.tl.ln, conf.l2) implicit val (tl, ln, l2) = (conf.tl, conf.tl.ln, conf.l2)
val io = new Bundle { val io = new Bundle {
@ -15,11 +15,11 @@ class FPGAOuterMemorySystem(htif_width: Int, clientEndpoints: Seq[ClientCoherenc
val mem = new ioMem val mem = new ioMem
} }
require(clientEndpoints.length == ln.nClients)
val masterEndpoints = (0 until ln.nMasters).map(i => Module(new L2CoherenceAgent(i))) val masterEndpoints = (0 until ln.nMasters).map(i => Module(new L2CoherenceAgent(i)))
val net = Module(new ReferenceChipCrossbarNetwork(masterEndpoints++clientEndpoints)) val net = Module(new ReferenceChipCrossbarNetwork)
net.io zip (masterEndpoints.map(_.io.client) ++ io.tiles :+ io.htif) map { case (net, end) => net <> end } net.io.clients zip (io.tiles :+ io.htif) map { case (net, end) => net <> end }
net.io.masters zip (masterEndpoints.map(_.io.client)) map { case (net, end) => net <> end }
masterEndpoints.map{ _.io.incoherent zip io.incoherent map { case (m, c) => m := c } } masterEndpoints.map{ _.io.incoherent zip io.incoherent map { case (m, c) => m := c } }
val conv = Module(new MemIOUncachedTileLinkIOConverter(2)) val conv = Module(new MemIOUncachedTileLinkIOConverter(2))
@ -35,7 +35,7 @@ class FPGAOuterMemorySystem(htif_width: Int, clientEndpoints: Seq[ClientCoherenc
conv.io.mem.resp <> Queue(io.mem.resp) conv.io.mem.resp <> Queue(io.mem.resp)
} }
class FPGAUncore(htif_width: Int, tileList: Seq[ClientCoherenceAgent])(implicit conf: UncoreConfiguration) extends Module class FPGAUncore(htif_width: Int)(implicit conf: UncoreConfiguration) extends Module
{ {
implicit val (tl, ln) = (conf.tl, conf.tl.ln) implicit val (tl, ln) = (conf.tl, conf.tl.ln)
val io = new Bundle { val io = new Bundle {
@ -46,7 +46,7 @@ class FPGAUncore(htif_width: Int, tileList: Seq[ClientCoherenceAgent])(implicit
val incoherent = Vec.fill(conf.nTiles){Bool()}.asInput val incoherent = Vec.fill(conf.nTiles){Bool()}.asInput
} }
val htif = Module(new HTIF(htif_width, CSRs.reset, conf.nSCR)) val htif = Module(new HTIF(htif_width, CSRs.reset, conf.nSCR))
val outmemsys = Module(new FPGAOuterMemorySystem(htif_width, tileList :+ htif)) val outmemsys = Module(new FPGAOuterMemorySystem(htif_width))
val incoherentWithHtif = (io.incoherent :+ Bool(true).asInput) val incoherentWithHtif = (io.incoherent :+ Bool(true).asInput)
outmemsys.io.incoherent := incoherentWithHtif outmemsys.io.incoherent := incoherentWithHtif
htif.io.cpu <> io.htif htif.io.cpu <> io.htif
@ -85,7 +85,7 @@ class FPGATop extends Module {
val ntiles = 1 val ntiles = 1
val nbanks = 1 val nbanks = 1
val nmshrs = 2 val nmshrs = 2
implicit val ln = LogicalNetworkConfiguration(ntiles+nbanks+1, log2Up(ntiles)+1, nbanks, ntiles+1) implicit val ln = LogicalNetworkConfiguration(log2Up(ntiles)+1, nbanks, ntiles+1)
implicit val tl = TileLinkConfiguration(co, ln, log2Up(1+8), 2*log2Up(nmshrs*ntiles+1), MEM_DATA_BITS) implicit val tl = TileLinkConfiguration(co, ln, log2Up(1+8), 2*log2Up(nmshrs*ntiles+1), MEM_DATA_BITS)
implicit val l2 = L2CoherenceAgentConfiguration(tl, 1, 8) implicit val l2 = L2CoherenceAgentConfiguration(tl, 1, 8)
implicit val uc = UncoreConfiguration(l2, tl, ntiles, nbanks, bankIdLsb = 5, nSCR = 64) implicit val uc = UncoreConfiguration(l2, tl, ntiles, nbanks, bankIdLsb = 5, nSCR = 64)
@ -100,7 +100,7 @@ class FPGATop extends Module {
val resetSigs = Vec.fill(uc.nTiles){Bool()} val resetSigs = Vec.fill(uc.nTiles){Bool()}
val tileList = (0 until uc.nTiles).map(r => Module(new Tile(resetSignal = resetSigs(r))(rc))) val tileList = (0 until uc.nTiles).map(r => Module(new Tile(resetSignal = resetSigs(r))(rc)))
val uncore = Module(new FPGAUncore(htif_width, tileList)) val uncore = Module(new FPGAUncore(htif_width))
for (i <- 0 until uc.nTiles) { for (i <- 0 until uc.nTiles) {
val hl = uncore.io.htif(i) val hl = uncore.io.htif(i)

117
src/main/scala/network.scala
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@ -3,25 +3,26 @@ package referencechip
import Chisel._ import Chisel._
import uncore._ import uncore._
import scala.reflect._ import scala.reflect._
import scala.reflect.runtime.universe._
object TileLinkHeaderAppender { object TileLinkHeaderAppender {
def apply[T <: SourcedMessage with HasPhysicalAddress, U <: SourcedMessage with HasTileLinkData](in: ClientSourcedDataIO[LogicalNetworkIO[T],LogicalNetworkIO[U]], clientId: Int, nBanks: Int, addrConvert: Bits => UInt)(implicit conf: TileLinkConfiguration) = { def apply[T <: ClientSourcedMessage with HasPhysicalAddress, U <: ClientSourcedMessage with HasTileLinkData](in: PairedDataIO[LogicalNetworkIO[T],LogicalNetworkIO[U]], clientId: Int, nBanks: Int, addrConvert: Bits => UInt)(implicit conf: TileLinkConfiguration) = {
val shim = Module(new TileLinkHeaderAppender(in.meta.bits.payload, in.data.bits.payload, clientId, nBanks, addrConvert)) val shim = Module(new TileLinkHeaderAppender(in.meta.bits.payload, in.data.bits.payload, clientId, nBanks, addrConvert))
shim.io.in <> in shim.io.in <> in
shim.io.out shim.io.out
} }
def apply[T <: SourcedMessage with HasPhysicalAddress](in: ClientSourcedFIFOIO[LogicalNetworkIO[T]], clientId: Int, nBanks: Int, addrConvert: Bits => UInt)(implicit conf: TileLinkConfiguration) = { def apply[T <: ClientSourcedMessage with HasPhysicalAddress](in: DecoupledIO[LogicalNetworkIO[T]], clientId: Int, nBanks: Int, addrConvert: Bits => UInt)(implicit conf: TileLinkConfiguration) = {
val shim = Module(new TileLinkHeaderAppender(in.bits.payload.clone, new AcquireData, clientId, nBanks, addrConvert)) val shim = Module(new TileLinkHeaderAppender(in.bits.payload.clone, new AcquireData, clientId, nBanks, addrConvert))
shim.io.in.meta <> in shim.io.in.meta <> in
shim.io.out.meta shim.io.out.meta
} }
} }
class TileLinkHeaderAppender[T <: SourcedMessage with HasPhysicalAddress, U <: SourcedMessage with HasTileLinkData](mType: T, dType: U, clientId: Int, nBanks: Int, addrConvert: Bits => UInt)(implicit conf: TileLinkConfiguration) extends Module { class TileLinkHeaderAppender[T <: ClientSourcedMessage with HasPhysicalAddress, U <: ClientSourcedMessage with HasTileLinkData](mType: T, dType: U, clientId: Int, nBanks: Int, addrConvert: Bits => UInt)(implicit conf: TileLinkConfiguration) extends Module {
implicit val ln = conf.ln implicit val ln = conf.ln
val io = new Bundle { val io = new Bundle {
val in = new ClientSourcedDataIO(new LogicalNetworkIO(mType), new LogicalNetworkIO(dType)).flip val in = new PairedDataIO(new LogicalNetworkIO(mType), new LogicalNetworkIO(dType)).flip
val out = new ClientSourcedDataIO(new LogicalNetworkIO(mType), new LogicalNetworkIO(dType)) val out = new PairedDataIO(new LogicalNetworkIO(mType), new LogicalNetworkIO(dType))
} }
val meta_q = Queue(io.in.meta) val meta_q = Queue(io.in.meta)
@ -93,11 +94,21 @@ class MemIOUncachedTileLinkIOConverter(qDepth: Int)(implicit conf: TileLinkConfi
io.mem.req_data <> mem_data_q.io.deq io.mem.req_data <> mem_data_q.io.deq
} }
class ReferenceChipCrossbarNetwork(endpoints: Seq[CoherenceAgentRole])(implicit conf: UncoreConfiguration) extends LogicalNetwork[TileLinkIO](endpoints)(conf.tl.ln) { class ReferenceChipCrossbarNetwork(implicit conf: UncoreConfiguration) extends LogicalNetwork[TileLinkIO]()(conf.tl.ln) {
implicit val (tl, ln, co) = (conf.tl, conf.tl.ln, conf.tl.co) implicit val (tl, ln, co) = (conf.tl, conf.tl.ln, conf.tl.co)
val io = Vec(endpoints.map(_ match { case t:ClientCoherenceAgent => {(new TileLinkIO).flip}; case h:MasterCoherenceAgent => {new TileLinkIO}})) val io = new Bundle {
val clients = Vec.fill(ln.nClients){(new TileLinkIO).flip}
val masters = Vec.fill(ln.nMasters){new TileLinkIO}
}
implicit val pconf = new PhysicalNetworkConfiguration(ln.nEndpoints, ln.idBits) // Same config for all networks implicit val pconf = new PhysicalNetworkConfiguration(ln.nEndpoints, ln.idBits) // Same config for all networks
// Actually instantiate the particular networks required for TileLink
val acqNet = Module(new PairedCrossbar(new Acquire, new AcquireData, REFILL_CYCLES, (acq: PhysicalNetworkIO[Acquire]) => co.messageHasData(acq.payload)))
val relNet = Module(new PairedCrossbar(new Release, new ReleaseData, REFILL_CYCLES, (rel: PhysicalNetworkIO[Release]) => co.messageHasData(rel.payload)))
val probeNet = Module(new BasicCrossbar(new Probe))
val grantNet = Module(new BasicCrossbar(new Grant))
val ackNet = Module(new BasicCrossbar(new GrantAck))
// Aliases for the various network IO bundle types // Aliases for the various network IO bundle types
type FBCIO[T <: Data] = DecoupledIO[PhysicalNetworkIO[T]] type FBCIO[T <: Data] = DecoupledIO[PhysicalNetworkIO[T]]
type FLNIO[T <: Data] = DecoupledIO[LogicalNetworkIO[T]] type FLNIO[T <: Data] = DecoupledIO[LogicalNetworkIO[T]]
@ -163,61 +174,53 @@ class ReferenceChipCrossbarNetwork(endpoints: Seq[CoherenceAgentRole])(implicit
phys_in.valid := Bool(false) phys_in.valid := Bool(false)
} }
// Use reflection to determine whether a particular endpoint should be def doFIFOHookup[T <: Data](isEndpointSourceOfMessage: Boolean, physIn: FBCIO[T], physOut: FBCIO[T], logIO: FLNIO[T], inShim: ToCrossbar[T], outShim: FromCrossbar[T]) = {
// hooked up as an [input/output] for a FIFO nework that is transmiitting if(isEndpointSourceOfMessage) doFIFOInputHookup(physIn, physOut, logIO, inShim)
// [client/master]-sourced messages. else doFIFOOutputHookup(physIn, physOut, logIO, outShim)
def doFIFOHookup[S <: CoherenceAgentRole: ClassTag, T <: Data](end: CoherenceAgentRole, phys_in: FBCIO[T], phys_out: FBCIO[T], log_io: FLNIO[T], inShim: ToCrossbar[T], outShim: FromCrossbar[T]) = {
// Is end's type a subtype of S, the agent type associated with inputs?
if(classTag[S].runtimeClass.isInstance(end))
doFIFOInputHookup(phys_in, phys_out, log_io, inShim)
else
doFIFOOutputHookup(phys_in, phys_out, log_io, outShim)
} }
def doClientSourcedFIFOHookup[T <: Data](end: CoherenceAgentRole, phys_in: FBCIO[T], phys_out: FBCIO[T], log_io: FLNIO[T]) = //Hookup all instances of a particular subbundle of
doFIFOHookup[ClientCoherenceAgent, T](end, phys_in, phys_out, log_io, ClientToCrossbarShim, CrossbarToMasterShim) def doFIFOHookups[T <: Data: TypeTag](physIO: BasicCrossbarIO[T], getLogIO: TileLinkIO => FLNIO[T]) = {
typeTag[T].tpe match{
def doMasterSourcedFIFOHookup[T <: Data](end: CoherenceAgentRole, phys_in: FBCIO[T], phys_out: FBCIO[T], log_io: FLNIO[T]) = case t if t <:< typeTag[ClientSourcedMessage].tpe => {
doFIFOHookup[MasterCoherenceAgent, T](end, phys_in, phys_out, log_io, MasterToCrossbarShim, CrossbarToClientShim) io.masters.zipWithIndex.map{ case (i, id) => doFIFOHookup[T](false, physIO.in(id), physIO.out(id), getLogIO(i), ClientToCrossbarShim, CrossbarToMasterShim) }
io.clients.zipWithIndex.map{ case (i, id) => doFIFOHookup[T](true, physIO.in(id+ln.nMasters), physIO.out(id+ln.nMasters), getLogIO(i), ClientToCrossbarShim, CrossbarToMasterShim) }
// Use reflection to determine whether a particular endpoint should be }
// hooked up as an [input/output] for a Paired nework that is transmiitting case t if t <:< typeTag[MasterSourcedMessage].tpe => {
// [client/master]-sourced messages. io.masters.zipWithIndex.map{ case (i, id) => doFIFOHookup[T](true, physIO.in(id), physIO.out(id), getLogIO(i), MasterToCrossbarShim, CrossbarToClientShim) }
def doPairedDataHookup[S <: CoherenceAgentRole : ClassTag, T <: Data, R <: Data](end: CoherenceAgentRole, phys_in: PBCIO[T,R], phys_out: PBCIO[T,R], log_io: PLNIO[T,R], inShim: ToCrossbar[T], outShim: FromCrossbar[T], inShimD: ToCrossbar[R], outShimD: FromCrossbar[R]) = { io.clients.zipWithIndex.map{ case (i, id) => doFIFOHookup[T](false, physIO.in(id+ln.nMasters), physIO.out(id+ln.nMasters), getLogIO(i), MasterToCrossbarShim, CrossbarToClientShim) }
// Is end's type a subtype of S, the agent type associated with inputs? }
if(classTag[S].runtimeClass.isInstance(end)) { case _ => require(false, "Unknown message sourcing.")
doFIFOInputHookup[T](phys_in.meta, phys_out.meta, log_io.meta, inShim)
doFIFOInputHookup[R](phys_in.data, phys_out.data, log_io.data, inShimD)
} else {
doFIFOOutputHookup[T](phys_in.meta, phys_out.meta, log_io.meta, outShim)
doFIFOOutputHookup[R](phys_in.data, phys_out.data, log_io.data, outShimD)
} }
} }
def doClientSourcedPairedHookup[T <: Data, R <: Data](end: CoherenceAgentRole, phys_in: PBCIO[T,R], phys_out: PBCIO[T,R], log_io: PLNIO[T,R]) = def doPairedDataHookup[T <: Data, R <: Data](isEndpointSourceOfMessage: Boolean, physIn: PBCIO[T,R], physOut: PBCIO[T,R], logIO: PLNIO[T,R], inShim: ToCrossbar[T], outShim: FromCrossbar[T], inShimD: ToCrossbar[R], outShimD: FromCrossbar[R]) = {
doPairedDataHookup[ClientCoherenceAgent, T, R](end, phys_in, phys_out, log_io, ClientToCrossbarShim, CrossbarToMasterShim, ClientToCrossbarShim, CrossbarToMasterShim) if(isEndpointSourceOfMessage) {
doFIFOInputHookup[T](physIn.meta, physOut.meta, logIO.meta, inShim)
doFIFOInputHookup[R](physIn.data, physOut.data, logIO.data, inShimD)
} else {
doFIFOOutputHookup[T](physIn.meta, physOut.meta, logIO.meta, outShim)
doFIFOOutputHookup[R](physIn.data, physOut.data, logIO.data, outShimD)
}
}
def doMasterSourcedPairedHookup[T <: Data, R <: Data](end: CoherenceAgentRole, phys_in: PBCIO[T,R], phys_out: PBCIO[T,R], log_io: PLNIO[T,R]) = def doPairedDataHookups[T <: Data: TypeTag, R <: Data](physIO: PairedCrossbarIO[T,R], getLogIO: TileLinkIO => PLNIO[T,R]) = {
doPairedDataHookup[MasterCoherenceAgent, T, R](end, phys_in, phys_out, log_io, MasterToCrossbarShim, CrossbarToClientShim, MasterToCrossbarShim, CrossbarToClientShim) typeTag[T].tpe match{
case t if t <:< typeTag[ClientSourcedMessage].tpe => {
io.masters.zipWithIndex.map{ case (i, id) => doPairedDataHookup[T,R](false, physIO.in(id), physIO.out(id), getLogIO(i), ClientToCrossbarShim, CrossbarToMasterShim, ClientToCrossbarShim, CrossbarToMasterShim) }
io.clients.zipWithIndex.map{ case (i, id) => doPairedDataHookup[T,R](true, physIO.in(id+ln.nMasters), physIO.out(id+ln.nMasters), getLogIO(i), ClientToCrossbarShim, CrossbarToMasterShim, ClientToCrossbarShim, CrossbarToMasterShim) }
}
case t if t <:< typeTag[MasterSourcedMessage].tpe => {
io.masters.zipWithIndex.map{ case (i, id) => doPairedDataHookup[T,R](true, physIO.in(id), physIO.out(id), getLogIO(i), MasterToCrossbarShim, CrossbarToClientShim, MasterToCrossbarShim, CrossbarToClientShim) }
io.clients.zipWithIndex.map{ case (i, id) => doPairedDataHookup[T,R](false, physIO.in(id+ln.nMasters), physIO.out(id+ln.nMasters), getLogIO(i), MasterToCrossbarShim, CrossbarToClientShim, MasterToCrossbarShim, CrossbarToClientShim) }
}
case _ => require(false, "Unknown message sourcing.")
}
}
doPairedDataHookups(acqNet.io, (tl: TileLinkIO) => tl.acquire)
// Actually instantiate the particular networks required for TileLink doPairedDataHookups(relNet.io, (tl: TileLinkIO) => tl.release)
def acqHasData(acq: PhysicalNetworkIO[Acquire]) = co.messageHasData(acq.payload) doFIFOHookups(probeNet.io, (tl: TileLinkIO) => tl.probe)
val acq_net = Module(new PairedCrossbar(new Acquire, new AcquireData, REFILL_CYCLES, acqHasData _)) doFIFOHookups(grantNet.io, (tl: TileLinkIO) => tl.grant)
endpoints.zip(io).zipWithIndex.map{ case ((end, io), id) => doClientSourcedPairedHookup(end, acq_net.io.in(id), acq_net.io.out(id), io.acquire) } doFIFOHookups(ackNet.io, (tl: TileLinkIO) => tl.grant_ack)
def relHasData(rel: PhysicalNetworkIO[Release]) = co.messageHasData(rel.payload)
val rel_net = Module(new PairedCrossbar(new Release, new ReleaseData, REFILL_CYCLES, relHasData _))
endpoints.zip(io).zipWithIndex.map{ case ((end, io), id) => doClientSourcedPairedHookup(end, rel_net.io.in(id), rel_net.io.out(id), io.release) }
val probe_net = Module(new BasicCrossbar(new Probe))
endpoints.zip(io).zipWithIndex.map{ case ((end, io), id) => doMasterSourcedFIFOHookup(end, probe_net.io.in(id), probe_net.io.out(id), io.probe) }
val grant_net = Module(new BasicCrossbar(new Grant))
endpoints.zip(io).zipWithIndex.map{ case ((end, io), id) => doMasterSourcedFIFOHookup(end, grant_net.io.in(id), grant_net.io.out(id), io.grant) }
val ack_net = Module(new BasicCrossbar(new GrantAck))
endpoints.zip(io).zipWithIndex.map{ case ((end, io), id) => doClientSourcedFIFOHookup(end, ack_net.io.in(id), ack_net.io.out(id), io.grant_ack) }
val physicalNetworks = List(acq_net, rel_net, probe_net, grant_net, ack_net)
} }

2
uncore

@ -1 +1 @@
Subproject commit a58265755fcb90aebe5377cb9b7343732fd14b9a Subproject commit f2a0b435fd98f323b97c423c9cbcd0cb3d03a406