Zap conflicting TLB entries, preparing for superpage support
Superpages create the possibility that two entries in the TLB may match. This corresponds to a software bug, but we can't return complete garbage; we must return either the old translation or the new translation. This isn't compatible with the Mux1H approach. So, flush the TLB and report a miss on duplicate entries.
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@ -132,12 +132,19 @@ class TLB(entries: Int)(implicit edge: TLEdgeOut, p: Parameters) extends CoreMod
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plru.access(OHToUInt(hits(entries-1, 0)))
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plru.access(OHToUInt(hits(entries-1, 0)))
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}
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}
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// Superpages create the possibility that two entries in the TLB may match.
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// This corresponds to a software bug, but we can't return complete garbage;
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// we must return either the old translation or the new translation. This
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// isn't compatible with the Mux1H approach. So, flush the TLB and report
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// a miss on duplicate entries.
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val multipleHits = PopCountAtLeast(hits(entries-1, 0), 2)
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io.req.ready := state === s_ready
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io.req.ready := state === s_ready
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io.resp.xcpt_ld := bad_va || (~r_array & hits).orR
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io.resp.xcpt_ld := bad_va || (~r_array & hits).orR
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io.resp.xcpt_st := bad_va || (~w_array & hits).orR
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io.resp.xcpt_st := bad_va || (~w_array & hits).orR
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io.resp.xcpt_if := bad_va || (~x_array & hits).orR
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io.resp.xcpt_if := bad_va || (~x_array & hits).orR
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io.resp.cacheable := (c_array & hits).orR
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io.resp.cacheable := (c_array & hits).orR
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io.resp.miss := do_refill || tlb_miss
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io.resp.miss := do_refill || tlb_miss || multipleHits
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io.resp.ppn := Mux1H(hitsVec, ppns :+ passthrough_ppn)
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io.resp.ppn := Mux1H(hitsVec, ppns :+ passthrough_ppn)
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io.ptw.req.valid := state === s_request
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io.ptw.req.valid := state === s_request
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@ -169,7 +176,7 @@ class TLB(entries: Int)(implicit edge: TLEdgeOut, p: Parameters) extends CoreMod
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state := s_ready
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state := s_ready
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}
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}
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when (io.ptw.invalidate) {
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when (io.ptw.invalidate || multipleHits) {
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valid := 0
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valid := 0
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}
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}
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}
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}
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