From 37fd11870c1b8a48f0c26623de3744f42304e721 Mon Sep 17 00:00:00 2001 From: Howard Mao Date: Wed, 13 Jul 2016 12:11:43 -0700 Subject: [PATCH] fix up ReorderQueue CAM --- junctions/src/main/scala/util.scala | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/junctions/src/main/scala/util.scala b/junctions/src/main/scala/util.scala index f30f1c65..f7a19ec8 100644 --- a/junctions/src/main/scala/util.scala +++ b/junctions/src/main/scala/util.scala @@ -186,17 +186,17 @@ class ReorderQueue[T <: Data](dType: T, tagWidth: Int, size: Option[Int] = None) val actualSize = size.getOrElse(tagSpaceSize) if (tagSpaceSize > actualSize) { - val roq_data = Mem(actualSize, dType) + val roq_data = Reg(Vec(actualSize, dType)) val roq_tags = Reg(Vec(actualSize, UInt(width = tagWidth))) val roq_free = Reg(init = Vec.fill(actualSize)(Bool(true))) val roq_enq_addr = PriorityEncoder(roq_free) val roq_matches = roq_tags.zip(roq_free) .map { case (tag, free) => tag === io.deq.tag && !free } - val roq_deq_addr = PriorityEncoder(roq_matches) + val roq_deq_onehot = PriorityEncoderOH(roq_matches) io.enq.ready := roq_free.reduce(_ || _) - io.deq.data := roq_data(roq_deq_addr) + io.deq.data := Mux1H(roq_deq_onehot, roq_data) io.deq.matches := roq_matches.reduce(_ || _) when (io.enq.valid && io.enq.ready) { @@ -206,10 +206,10 @@ class ReorderQueue[T <: Data](dType: T, tagWidth: Int, size: Option[Int] = None) } when (io.deq.valid) { - roq_free(roq_deq_addr) := Bool(true) + roq_free(OHToUInt(roq_deq_onehot)) := Bool(true) } - println("Warning: inferring a CAM for ReorderQueue") + println(s"Warning - using a CAM for ReorderQueue, tagBits: ${tagWidth} size: ${actualSize}") } else { val roq_data = Mem(tagSpaceSize, dType) val roq_free = Reg(init = Vec.fill(tagSpaceSize)(Bool(true)))