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fix comparator Chisel2 compilation issue

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This commit is contained in:
Howard Mao 2016-06-14 18:36:38 -07:00
parent b7c0d0cb4d
commit 377de06b72
1 changed files with 19 additions and 21 deletions
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34
groundtest/src/main/scala/comparator.scala
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@ -45,9 +45,8 @@ object LFSR64
object NoiseMaker object NoiseMaker
{ {
def apply(wide: Int, increment: Bool = Bool(true)): UInt = { def apply(wide: Int, increment: Bool = Bool(true)): UInt = {
val output = Wire(Vec((wide+63)/64, UInt())) val lfsrs = Seq.fill((wide+63)/64) { LFSR64() }
output.zipWithIndex.foreach { case (v,i) => v := LFSR64() } Cat(lfsrs)(wide-1,0)
output.toBits()(wide-1, 0)
} }
} }
@ -120,28 +119,27 @@ class ComparatorSource(implicit val p: Parameters) extends Module
val getPrefetch = GetPrefetch(client_xact_id, addr_block) val getPrefetch = GetPrefetch(client_xact_id, addr_block)
val optAtomic = if (atomics) putAtomic else put val optAtomic = if (atomics) putAtomic else put
// Generate a random a_type
io.out.bits := (new Acquire).fromBits(MuxLookup(NoiseMaker(3), get.toBits, Array(
UInt("b000") -> get.toBits,
UInt("b001") -> getBlock.toBits,
UInt("b010") -> put.toBits,
UInt("b011") -> putBlock.toBits,
UInt("b100") -> optAtomic.toBits,
UInt("b101") -> getPrefetch.toBits,
UInt("b110") -> putPrefetch.toBits)))
// We must initially putBlock all of memory to have a consistent starting state // We must initially putBlock all of memory to have a consistent starting state
val final_addr_block = addr_block_mask + UInt(1) val final_addr_block = addr_block_mask + UInt(1)
val wipe_addr_block = RegInit(UInt(0, width = tlBlockAddrBits)) val wipe_addr_block = RegInit(UInt(0, width = tlBlockAddrBits))
val done_wipe = wipe_addr_block === final_addr_block val done_wipe = wipe_addr_block === final_addr_block
io.out.bits := Mux(!done_wipe,
// Override whatever else we were going to do if we are wiping // Override whatever else we were going to do if we are wiping
when (!done_wipe) { PutBlock(client_xact_id, wipe_addr_block, UInt(0), data),
io.out.bits := PutBlock(client_xact_id, wipe_addr_block, UInt(0), data, SInt(-1, tlDataBytes).asUInt) // Generate a random a_type
when (valid) { MuxBundle(NoiseMaker(3), get, Array(
UInt("b000") -> get,
UInt("b001") -> getBlock,
UInt("b010") -> put,
UInt("b011") -> putBlock,
UInt("b100") -> optAtomic,
UInt("b101") -> getPrefetch,
UInt("b110") -> putPrefetch)))
when (!done_wipe && valid) {
wipe_addr_block := wipe_addr_block + UInt(1) wipe_addr_block := wipe_addr_block + UInt(1)
} }
}
} }
class ComparatorClient(val target: Long)(implicit val p: Parameters) extends Module class ComparatorClient(val target: Long)(implicit val p: Parameters) extends Module
@ -250,7 +248,7 @@ class ComparatorSink(implicit val p: Parameters) extends Module
def check(g: Grant) = { def check(g: Grant) = {
assert (g.is_builtin_type, "grant not builtin") assert (g.is_builtin_type, "grant not builtin")
assert (base.g_type === g.g_type, "g_type mismatch") assert (base.g_type === g.g_type, "g_type mismatch")
assert (base.addr_beat === g.addr_beat || !g.is(Grant.getDataBlockType), "addr_beat mismatch") assert (base.addr_beat === g.addr_beat || !g.hasData(), "addr_beat mismatch")
assert (base.data === g.data || !g.hasData(), "data mismatch") assert (base.data === g.data || !g.hasData(), "data mismatch")
} }
when (all_valid) { when (all_valid) {