riscv/rocket-chip
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coreplex: move CacheCork in front of SBus

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Continue to not allow caches to cache ROMs.
Update TinyConfig and WithStatelessBridge.
This commit is contained in:
Henry Cook committed 2017-10-10 16:24:32 -07:00
1 parent 8f5f80f958
commit 37406706b4
4 files changed
+33 -34
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src/main/scala/system/Configs.scala
+1 -1
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@@ -66,7 +66,7 @@ class DualCoreConfig extends Config(
class TinyConfig extends Config(
new WithNMemoryChannels(0) ++
new WithStatelessBridge ++
new WithNTinyCores(1) ++
new With1TinyCore ++
new BaseConfig)
class DefaultFPGAConfig extends Config(new BaseConfig)