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Factor out most of HasRocketTiles into HasTiles

This commit is contained in:
Andrew Waterman 2017-10-07 17:29:50 -07:00
parent 70a4127cb8
commit 36c39d01e4
2 changed files with 45 additions and 41 deletions

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@ -7,7 +7,7 @@ import freechips.rocketchip.config.Parameters
import freechips.rocketchip.diplomacy._ import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._ import freechips.rocketchip.tilelink._
import freechips.rocketchip.devices.tilelink._ import freechips.rocketchip.devices.tilelink._
import freechips.rocketchip.tile.{BaseTile, TileParams} import freechips.rocketchip.tile.{BaseTile, TileParams, SharedMemoryTLEdge, HasExternallyDrivenTileConstants}
import freechips.rocketchip.devices.debug.{HasPeripheryDebug, HasPeripheryDebugModuleImp} import freechips.rocketchip.devices.debug.{HasPeripheryDebug, HasPeripheryDebugModuleImp}
import freechips.rocketchip.util._ import freechips.rocketchip.util._
@ -44,7 +44,7 @@ trait HasTiles extends HasSystemBus {
(t.core.nLocalInterrupts > 0).option(LazyModule(new IntXbar).intnode) (t.core.nLocalInterrupts > 0).option(LazyModule(new IntXbar).intnode)
} }
val rocket_tiles: Seq[BaseTile] val tiles: Seq[BaseTile]
} }
/** Base Coreplex class with no peripheral devices or ports added */ /** Base Coreplex class with no peripheral devices or ports added */
@ -105,6 +105,46 @@ abstract class BaseCoreplex(implicit p: Parameters) extends BareCoreplex
} }
} }
class ClockedTileInputs(implicit val p: Parameters) extends ParameterizedBundle
with HasExternallyDrivenTileConstants
with Clocked
trait HasTilesBundle {
val tile_inputs: Vec[ClockedTileInputs]
}
trait HasTilesModuleImp extends LazyModuleImp
with HasTilesBundle
with HasResetVectorWire {
val outer: HasTiles
def resetVectorBits: Int = {
// Consider using the minimum over all widths, rather than enforcing homogeneity
val vectors = outer.tiles.map(_.module.io.reset_vector)
require(vectors.tail.forall(_.getWidth == vectors.head.getWidth))
vectors.head.getWidth
}
val tile_inputs = Wire(Vec(outer.nRocketTiles, new ClockedTileInputs()(p.alterPartial {
case SharedMemoryTLEdge => outer.sharedMemoryTLEdge
})))
// Unconditionally wire up the non-diplomatic tile inputs
outer.tiles.map(_.module).zip(tile_inputs).foreach { case(tile, wire) =>
tile.clock := wire.clock
tile.reset := wire.reset
tile.io.hartid := wire.hartid
tile.io.reset_vector := wire.reset_vector
}
// Default values for tile inputs; may be overriden in other traits
tile_inputs.zip(outer.hartIdList).foreach { case(wire, i) =>
wire.clock := clock
wire.reset := reset
wire.hartid := UInt(i)
wire.reset_vector := global_reset_vector
}
}
abstract class BaseCoreplexModule[+L <: BaseCoreplex](_outer: L) extends BareCoreplexModule(_outer) { abstract class BaseCoreplexModule[+L <: BaseCoreplex](_outer: L) extends BareCoreplexModule(_outer) {
println("Generated Address Map") println("Generated Address Map")
private val aw = (outer.sharedMemoryTLEdge.bundle.addressBits-1)/4 + 1 private val aw = (outer.sharedMemoryTLEdge.bundle.addressBits-1)/4 + 1

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@ -26,7 +26,7 @@ trait HasRocketTiles extends HasTiles
// Make a wrapper for each tile that will wire it to coreplex devices and crossbars, // Make a wrapper for each tile that will wire it to coreplex devices and crossbars,
// according to the specified type of clock crossing. // according to the specified type of clock crossing.
val rocket_tiles: Seq[BaseTile] = localIntNodes.zip(tileParams).map { case (lip, tp) => val tiles: Seq[BaseTile] = localIntNodes.zip(tileParams).map { case (lip, tp) =>
val pWithExtra = p.alterPartial { val pWithExtra = p.alterPartial {
case TileKey => tp case TileKey => tp
case BuildRoCC => tp.rocc case BuildRoCC => tp.rocc
@ -85,45 +85,9 @@ trait HasRocketTiles extends HasTiles
} }
} }
class ClockedRocketTileInputs(implicit val p: Parameters) extends ParameterizedBundle trait HasRocketTilesModuleImp extends HasTilesModuleImp
with HasExternallyDrivenTileConstants
with Clocked
trait HasRocketTilesBundle {
val rocket_tile_inputs: Vec[ClockedRocketTileInputs]
}
trait HasRocketTilesModuleImp extends LazyModuleImp
with HasRocketTilesBundle
with HasResetVectorWire
with HasPeripheryDebugModuleImp { with HasPeripheryDebugModuleImp {
val outer: HasTiles with HasPeripheryDebug val outer: HasRocketTiles
def resetVectorBits: Int = {
// Consider using the minimum over all widths, rather than enforcing homogeneity
val vectors = outer.rocket_tiles.map(_.module.io.reset_vector)
require(vectors.tail.forall(_.getWidth == vectors.head.getWidth))
vectors.head.getWidth
}
val rocket_tile_inputs = Wire(Vec(outer.nRocketTiles, new ClockedRocketTileInputs()(p.alterPartial {
case SharedMemoryTLEdge => outer.sharedMemoryTLEdge
})))
// Unconditionally wire up the non-diplomatic tile inputs
outer.rocket_tiles.map(_.module).zip(rocket_tile_inputs).foreach { case(tile, wire) =>
tile.clock := wire.clock
tile.reset := wire.reset
tile.io.hartid := wire.hartid
tile.io.reset_vector := wire.reset_vector
}
// Default values for tile inputs; may be overriden in other traits
rocket_tile_inputs.zip(outer.hartIdList).foreach { case(wire, i) =>
wire.clock := clock
wire.reset := reset
wire.hartid := UInt(i)
wire.reset_vector := global_reset_vector
}
} }
class RocketCoreplex(implicit p: Parameters) extends BaseCoreplex class RocketCoreplex(implicit p: Parameters) extends BaseCoreplex