riscv/rocket-chip
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Bypass scoreboard to reduce MMIO latency

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Andrew Waterman 2017-04-22 22:13:40 -07:00 committed by Andrew Waterman
parent 845e6f7458
commit 36a7971975
1 changed files with 1 additions and 1 deletions
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src/main/scala/rocket/Rocket.scala
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@ -520,7 +520,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p)
val sboard = new Scoreboard(32, true)
sboard.clear(ll_wen, ll_waddr)
val id_sboard_hazard = checkHazards(hazard_targets, sboard.read _)
val id_sboard_hazard = checkHazards(hazard_targets, rd => sboard.read(rd) && !(ll_wen && ll_waddr === rd))
sboard.set(wb_set_sboard && wb_wen, wb_waddr)
// stall for RAW/WAW hazards on CSRs, loads, AMOs, and mul/div in execute stage.