riscv/rocket-chip
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OHToUInt instead of PriorityEncoder on Acq/RelMatches signals in L2Bank

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This commit is contained in:
Henry Cook 2015-11-03 14:31:35 -08:00
parent baa2544651
commit 3698153535
1 changed files with 6 additions and 2 deletions
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8
uncore/src/main/scala/cache.scala
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@ -316,7 +316,7 @@ class TSHRFile(implicit p: Parameters) extends L2HellaCacheModule()(p)
val acquireMatches = Vec(trackerList.map(_.io.has_acquire_match)).toBits val acquireMatches = Vec(trackerList.map(_.io.has_acquire_match)).toBits
val acquireReadys = Vec(trackerAcquireIOs.map(_.ready)).toBits val acquireReadys = Vec(trackerAcquireIOs.map(_.ready)).toBits
val acquire_idx = Mux(acquireMatches.orR, val acquire_idx = Mux(acquireMatches.orR,
PriorityEncoder(acquireMatches), OHToUInt(acquireMatches),
PriorityEncoder(acquireReadys)) PriorityEncoder(acquireReadys))
val block_acquires = acquireConflicts.orR val block_acquires = acquireConflicts.orR
io.inner.acquire.ready := acquireReadys.orR && !block_acquires io.inner.acquire.ready := acquireReadys.orR && !block_acquires
@ -325,18 +325,22 @@ class TSHRFile(implicit p: Parameters) extends L2HellaCacheModule()(p)
tracker.bits := io.inner.acquire.bits tracker.bits := io.inner.acquire.bits
tracker.valid := io.inner.acquire.valid && !block_acquires && (acquire_idx === UInt(i)) tracker.valid := io.inner.acquire.valid && !block_acquires && (acquire_idx === UInt(i))
} }
assert(PopCount(acquireMatches) <= UInt(1),
"At most a single tracker should match for any given Acquire")
// Wire releases from clients // Wire releases from clients
val trackerReleaseIOs = trackerList.map(_.io.inner.release) :+ wb.io.inner.release val trackerReleaseIOs = trackerList.map(_.io.inner.release) :+ wb.io.inner.release
val releaseReadys = Vec(trackerReleaseIOs.map(_.ready)).toBits val releaseReadys = Vec(trackerReleaseIOs.map(_.ready)).toBits
val releaseMatches = Vec(trackerList.map(_.io.has_release_match) :+ wb.io.has_release_match).toBits val releaseMatches = Vec(trackerList.map(_.io.has_release_match) :+ wb.io.has_release_match).toBits
val release_idx = PriorityEncoder(releaseMatches) val release_idx = OHToUInt(releaseMatches)
io.inner.release.ready := releaseReadys(release_idx) io.inner.release.ready := releaseReadys(release_idx)
trackerReleaseIOs.zipWithIndex.foreach { trackerReleaseIOs.zipWithIndex.foreach {
case(tracker, i) => case(tracker, i) =>
tracker.bits := io.inner.release.bits tracker.bits := io.inner.release.bits
tracker.valid := io.inner.release.valid && (release_idx === UInt(i)) tracker.valid := io.inner.release.valid && (release_idx === UInt(i))
} }
assert(PopCount(releaseMatches) <= UInt(nReleaseTransactors),
"At most a single tracker should match for any given Release")
assert(!(io.inner.release.valid && !releaseMatches.orR), assert(!(io.inner.release.valid && !releaseMatches.orR),
"Non-voluntary release should always have a Tracker waiting for it.") "Non-voluntary release should always have a Tracker waiting for it.")