riscv/rocket-chip
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Set complete unconditionally

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Wesley W. Terpstra 2017-06-30 10:15:53 -07:00 committed by GitHub
parent 4e9f65b2ef
commit 367d4aebe6
1 changed files with 3 additions and 2 deletions
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src/main/scala/uncore/devices/Plic.scala
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@ -198,8 +198,9 @@ class TLPLIC(params: PLICParams)(implicit p: Parameters) extends LazyModule
// (Note -- PLIC doesn't care which hart writes the register) // (Note -- PLIC doesn't care which hart writes the register)
val completer = Wire(Vec(nHarts, Bool())) val completer = Wire(Vec(nHarts, Bool()))
val irq = data.extract(log2Ceil(nDevices+1)-1, 0) val irq = data.extract(log2Ceil(nDevices+1)-1, 0)
when (completer.reduce(_ || _)) { val completedDevs = Mux(completer.reduce(_ || _), UIntToOH(irq, nDevices+1), UInt(0))
gateways(irq).complete := Bool(false) (gateways zip completedDevs.toBools) foreach { case (g, c) =>
g.complete := c
} }
val hartRegFields = Seq.tabulate(nHarts) { i => val hartRegFields = Seq.tabulate(nHarts) { i =>