Merge pull request #1100 from freechipsproject/disable-local-amos
Provide option to support AMOs only on I/O, not DTIM/D$
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commit
35d377d122
@ -76,7 +76,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
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val eccBits = eccBytes * 8
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require(isPow2(eccBytes) && eccBytes <= wordBytes)
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require(eccBytes == 1 || !dECC.isInstanceOf[IdentityCode])
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val usingRMW = eccBytes > 1 || usingAtomics
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val usingRMW = eccBytes > 1 || usingAtomicsInCache
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// tags
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val replacer = cacheParams.replacement
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@ -688,11 +688,11 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
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if (usingRMW) {
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val amoalu = Module(new AMOALU(xLen))
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amoalu.io.mask := pstore1_mask
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amoalu.io.cmd := (if (usingAtomics) pstore1_cmd else M_XWR)
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amoalu.io.cmd := (if (usingAtomicsInCache) pstore1_cmd else M_XWR)
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amoalu.io.lhs := s2_data_word
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amoalu.io.rhs := pstore1_data
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pstore1_storegen_data := amoalu.io.out
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} else {
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} else if (!usingAtomics) {
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assert(!(s1_valid_masked && s1_read && s1_write), "unsupported D$ operation")
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}
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when (s2_correct) { pstore1_storegen_data := s2_data_word_corrected }
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@ -18,6 +18,7 @@ case class RocketCoreParams(
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useUser: Boolean = false,
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useDebug: Boolean = true,
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useAtomics: Boolean = true,
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useAtomicsOnlyForIO: Boolean = false,
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useCompressed: Boolean = true,
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nLocalInterrupts: Int = 0,
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nBreakpoints: Int = 1,
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@ -100,7 +100,7 @@ trait CanHaveScratchpad extends HasHellaCache with HasICacheFrontend {
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val cacheBlockBytes = p(CacheBlockBytes)
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val scratch = tileParams.dcache.flatMap { d => d.scratch.map(s =>
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LazyModule(new ScratchpadSlavePort(AddressSet(s, d.dataScratchpadBytes-1), xBytes, tileParams.core.useAtomics)))
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LazyModule(new ScratchpadSlavePort(AddressSet(s, d.dataScratchpadBytes-1), xBytes, tileParams.core.useAtomics && !tileParams.core.useAtomicsOnlyForIO)))
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}
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val intOutputNode = tileParams.core.tileControlAddr.map(dummy => IntIdentityNode())
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@ -117,8 +117,8 @@ class TLB(instruction: Boolean, lgMaxSize: Int, nEntries: Int)(implicit edge: TL
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val homogeneous = TLBPageLookup(edge.manager.managers, xLen, p(CacheBlockBytes), BigInt(1) << pgIdxBits)(mpu_physaddr).homogeneous
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val prot_r = fastCheck(_.supportsGet) && pmp.io.r
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val prot_w = fastCheck(_.supportsPutFull) && pmp.io.w
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val prot_al = fastCheck(_.supportsLogical) || cacheable
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val prot_aa = fastCheck(_.supportsArithmetic) || cacheable
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val prot_al = fastCheck(_.supportsLogical) || (cacheable && usingAtomicsInCache)
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val prot_aa = fastCheck(_.supportsArithmetic) || (cacheable && usingAtomicsInCache)
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val prot_x = fastCheck(_.executable) && pmp.io.x
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val prot_eff = fastCheck(Seq(RegionType.PUT_EFFECTS, RegionType.GET_EFFECTS) contains _.regionType)
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@ -190,7 +190,7 @@ class TLB(instruction: Boolean, lgMaxSize: Int, nEntries: Int)(implicit edge: TL
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(if (vpnBits == vpnBitsExtended) Bool(false)
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else (io.req.bits.vaddr.asSInt < 0.S) =/= (vpn.asSInt < 0.S))
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val lrscAllowed = Mux(Bool(usingDataScratchpad), 0.U, c_array)
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val lrscAllowed = Mux(Bool(usingDataScratchpad || usingAtomicsOnlyForIO), 0.U, c_array)
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val ae_array =
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Mux(misaligned, eff_array, 0.U) |
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Mux(Bool(usingAtomics) && io.req.bits.cmd.isOneOf(M_XLR, M_XSC), ~lrscAllowed, 0.U)
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@ -17,6 +17,7 @@ trait CoreParams {
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val useUser: Boolean
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val useDebug: Boolean
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val useAtomics: Boolean
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val useAtomicsOnlyForIO: Boolean
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val useCompressed: Boolean
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val mulDiv: Option[MulDivParams]
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val fpu: Option[FPUParams]
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@ -47,6 +48,8 @@ trait HasCoreParameters extends HasTileParameters {
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val usingMulDiv = coreParams.mulDiv.nonEmpty
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val usingFPU = coreParams.fpu.nonEmpty
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val usingAtomics = coreParams.useAtomics
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val usingAtomicsOnlyForIO = coreParams.useAtomicsOnlyForIO
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val usingAtomicsInCache = usingAtomics && !usingAtomicsOnlyForIO
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val usingCompressed = coreParams.useCompressed
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val retireWidth = coreParams.retireWidth
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