riscv/rocket-chip
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fix a width bug

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This commit is contained in:
Howard Mao 2016-07-15 18:46:20 -07:00
parent 6fc4236782
commit 359252fdc1
1 changed files with 1 additions and 1 deletions
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groundtest/src/main/scala/unittests/Drivers.scala
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@ -274,7 +274,7 @@ class PutBlockSweepDriver(val n: Int)(implicit p: Parameters)
state === s_get_resp && io.mem.grant.valid, tlDataBeats) state === s_get_resp && io.mem.grant.valid, tlDataBeats)
val (get_cnt, get_done) = Counter(get_beat_done, n) val (get_cnt, get_done) = Counter(get_beat_done, n)
val dataRep = tlDataBits / (log2Up(n) + tlBeatAddrBits) val dataRep = (tlDataBits - 1) / (log2Up(n) + tlBeatAddrBits) + 1
val put_data = Fill(dataRep, Cat(put_cnt, put_beat))(tlDataBits - 1, 0) val put_data = Fill(dataRep, Cat(put_cnt, put_beat))(tlDataBits - 1, 0)
val get_data = Fill(dataRep, Cat(get_cnt, get_beat))(tlDataBits - 1, 0) val get_data = Fill(dataRep, Cat(get_cnt, get_beat))(tlDataBits - 1, 0)