From 5d07733057183359757d25883a5a05b1d3ca0dcc Mon Sep 17 00:00:00 2001 From: Christopher Celio Date: Tue, 3 Mar 2015 16:40:39 -0800 Subject: [PATCH 1/2] Removed TLBPTWIO from the io.cpu bundle for icache/dcache --- rocket/src/main/scala/icache.scala | 8 ++++---- rocket/src/main/scala/nbdcache.scala | 6 +++--- rocket/src/main/scala/tile.scala | 4 ++-- 3 files changed, 9 insertions(+), 9 deletions(-) diff --git a/rocket/src/main/scala/icache.scala b/rocket/src/main/scala/icache.scala index 80d1ff02..ffdcd9ee 100644 --- a/rocket/src/main/scala/icache.scala +++ b/rocket/src/main/scala/icache.scala @@ -37,7 +37,6 @@ class CPUFrontendIO extends Bundle { val btb_update = Valid(new BTBUpdate) val bht_update = Valid(new BHTUpdate) val ras_update = Valid(new RASUpdate) - val ptw = new TLBPTWIO().flip val invalidate = Bool(OUTPUT) } @@ -45,6 +44,7 @@ class Frontend(btb_updates_out_of_order: Boolean = false) extends FrontendModule { val io = new Bundle { val cpu = new CPUFrontendIO().flip + val ptw = new TLBPTWIO() val mem = new UncachedTileLinkIO } @@ -94,9 +94,9 @@ class Frontend(btb_updates_out_of_order: Boolean = false) extends FrontendModule btb.io.btb_update := io.cpu.btb_update btb.io.bht_update := io.cpu.bht_update btb.io.ras_update := io.cpu.ras_update - btb.io.invalidate := io.cpu.invalidate || io.cpu.ptw.invalidate + btb.io.invalidate := io.cpu.invalidate || io.ptw.invalidate - tlb.io.ptw <> io.cpu.ptw + tlb.io.ptw <> io.ptw tlb.io.req.valid := !stall && !icmiss tlb.io.req.bits.vpn := s1_pc >> UInt(pgIdxBits) tlb.io.req.bits.asid := UInt(0) @@ -108,7 +108,7 @@ class Frontend(btb_updates_out_of_order: Boolean = false) extends FrontendModule icache.io.req.bits.idx := Mux(io.cpu.req.valid, io.cpu.req.bits.pc, npc) icache.io.invalidate := io.cpu.invalidate icache.io.req.bits.ppn := tlb.io.resp.ppn - icache.io.req.bits.kill := io.cpu.req.valid || tlb.io.resp.miss || icmiss || io.cpu.ptw.invalidate + icache.io.req.bits.kill := io.cpu.req.valid || tlb.io.resp.miss || icmiss || io.ptw.invalidate icache.io.resp.ready := !stall && !s1_same_block io.cpu.resp.valid := s2_valid && (s2_xcpt_if || icache.io.resp.valid) diff --git a/rocket/src/main/scala/nbdcache.scala b/rocket/src/main/scala/nbdcache.scala index e4d370b1..72829979 100644 --- a/rocket/src/main/scala/nbdcache.scala +++ b/rocket/src/main/scala/nbdcache.scala @@ -83,7 +83,6 @@ class HellaCacheIO extends CoreBundle { val resp = Valid(new HellaCacheResp).flip val replay_next = Valid(Bits(width = coreDCacheReqTagBits)).flip val xcpt = (new HellaCacheExceptions).asInput - val ptw = new TLBPTWIO().flip val ordered = Bool(INPUT) } @@ -596,6 +595,7 @@ class DataArray extends L1HellaCacheModule { class HellaCache extends L1HellaCacheModule { val io = new Bundle { val cpu = (new HellaCacheIO).flip + val ptw = new TLBPTWIO() val mem = new TileLinkIO } @@ -634,7 +634,7 @@ class HellaCache extends L1HellaCacheModule { val s1_readwrite = s1_read || s1_write || isPrefetch(s1_req.cmd) val dtlb = Module(new TLB) - dtlb.io.ptw <> io.cpu.ptw + dtlb.io.ptw <> io.ptw dtlb.io.req.valid := s1_valid_masked && s1_readwrite && !s1_req.phys dtlb.io.req.bits.passthrough := s1_req.phys dtlb.io.req.bits.asid := UInt(0) @@ -750,7 +750,7 @@ class HellaCache extends L1HellaCacheModule { lrsc_count := 0 } } - when (io.cpu.ptw.sret) { lrsc_count := 0 } + when (io.ptw.sret) { lrsc_count := 0 } val s2_data = Vec.fill(nWays){Bits(width = encRowBits)} for (w <- 0 until nWays) { diff --git a/rocket/src/main/scala/tile.scala b/rocket/src/main/scala/tile.scala index 4ad0897d..de188bdf 100644 --- a/rocket/src/main/scala/tile.scala +++ b/rocket/src/main/scala/tile.scala @@ -31,8 +31,8 @@ class RocketTile(resetSignal: Bool = null) extends Tile(resetSignal) { dcArb.io.requestor(1) <> core.io.dmem dcArb.io.mem <> dcache.io.cpu - ptw.io.requestor(0) <> icache.io.cpu.ptw - ptw.io.requestor(1) <> dcache.io.cpu.ptw + ptw.io.requestor(0) <> icache.io.ptw + ptw.io.requestor(1) <> dcache.io.ptw core.io.host <> io.host core.io.imem <> icache.io.cpu From 06dea3790a9a6b54ad514d8e0074f557e2e00a45 Mon Sep 17 00:00:00 2001 From: Christopher Celio Date: Tue, 3 Mar 2015 16:50:41 -0800 Subject: [PATCH 2/2] Removed sret from ptw; sret now comes thru io.cpu to dcache --- rocket/src/main/scala/ctrl.scala | 1 + rocket/src/main/scala/dpath.scala | 1 - rocket/src/main/scala/nbdcache.scala | 3 ++- rocket/src/main/scala/ptw.scala | 3 --- 4 files changed, 3 insertions(+), 5 deletions(-) diff --git a/rocket/src/main/scala/ctrl.scala b/rocket/src/main/scala/ctrl.scala index 1811e2bc..bb29c2ac 100644 --- a/rocket/src/main/scala/ctrl.scala +++ b/rocket/src/main/scala/ctrl.scala @@ -675,6 +675,7 @@ class Control extends CoreModule io.dmem.req.bits.cmd := ex_ctrl.mem_cmd io.dmem.req.bits.typ := ex_ctrl.mem_type io.dmem.req.bits.phys := Bool(false) + io.dmem.sret := io.dpath.sret io.rocc.cmd.valid := wb_rocc_val io.rocc.exception := wb_reg_xcpt && sr.er diff --git a/rocket/src/main/scala/dpath.scala b/rocket/src/main/scala/dpath.scala index d9013379..f5346b3b 100644 --- a/rocket/src/main/scala/dpath.scala +++ b/rocket/src/main/scala/dpath.scala @@ -177,7 +177,6 @@ class Datapath extends CoreModule io.ptw.ptbr := pcr.io.ptbr io.ptw.invalidate := pcr.io.fatc - io.ptw.sret := io.ctrl.sret io.ptw.status := pcr.io.status // memory stage diff --git a/rocket/src/main/scala/nbdcache.scala b/rocket/src/main/scala/nbdcache.scala index 72829979..9d3ca5b8 100644 --- a/rocket/src/main/scala/nbdcache.scala +++ b/rocket/src/main/scala/nbdcache.scala @@ -83,6 +83,7 @@ class HellaCacheIO extends CoreBundle { val resp = Valid(new HellaCacheResp).flip val replay_next = Valid(Bits(width = coreDCacheReqTagBits)).flip val xcpt = (new HellaCacheExceptions).asInput + val sret = Bool(OUTPUT) val ordered = Bool(INPUT) } @@ -750,7 +751,7 @@ class HellaCache extends L1HellaCacheModule { lrsc_count := 0 } } - when (io.ptw.sret) { lrsc_count := 0 } + when (io.cpu.sret) { lrsc_count := 0 } val s2_data = Vec.fill(nWays){Bits(width = encRowBits)} for (w <- 0 until nWays) { diff --git a/rocket/src/main/scala/ptw.scala b/rocket/src/main/scala/ptw.scala index cba40021..a165cfc0 100644 --- a/rocket/src/main/scala/ptw.scala +++ b/rocket/src/main/scala/ptw.scala @@ -17,13 +17,11 @@ class TLBPTWIO extends CoreBundle { val resp = Valid(new PTWResp).flip val status = new Status().asInput val invalidate = Bool(INPUT) - val sret = Bool(INPUT) } class DatapathPTWIO extends CoreBundle { val ptbr = UInt(INPUT, paddrBits) val invalidate = Bool(INPUT) - val sret = Bool(INPUT) val status = new Status().asInput } @@ -83,7 +81,6 @@ class PTW(n: Int) extends CoreModule io.requestor(i).resp.bits.perm := r_pte(8,3) io.requestor(i).resp.bits.ppn := resp_ppn.toUInt io.requestor(i).invalidate := io.dpath.invalidate - io.requestor(i).sret := io.dpath.sret io.requestor(i).status := io.dpath.status }