Remove legacy HTIF things
The SCR file is gone, too, because it is tightly coupled. The general concept could be revived as a module that somehow connects to (or is contained by) the debug module.
This commit is contained in:
Andrew Waterman
parent
f57524e0c1
commit
354b81c8fe
@ -83,8 +83,7 @@ class DmaTrackerIO(implicit p: Parameters) extends DmaBundle()(p) {
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class DmaManager(outstandingCSR: Int)(implicit p: Parameters)
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extends DmaModule()(p)
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with HasNastiParameters
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with HasAddrMapParameters
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with HasHtifParameters {
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with HasAddrMapParameters {
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val io = new Bundle {
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val ctrl = (new NastiIO).flip
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@ -168,7 +167,9 @@ class DmaManager(outstandingCSR: Int)(implicit p: Parameters)
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}
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val addrTable = Vec.tabulate(nDmaClients) { i =>
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UInt(addrMap(s"conf:csr$i").start + outstandingCSR * csrDataBytes)
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//UInt(addrMap(s"conf:csr$i").start + outstandingCSR * csrDataBytes)
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require(false, "CSR MMIO ports no longer exist")
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UInt(0)
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}
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io.mmio.ar.valid := Bool(false)
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@ -176,7 +177,7 @@ class DmaManager(outstandingCSR: Int)(implicit p: Parameters)
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io.mmio.aw.bits := NastiWriteAddressChannel(
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id = UInt(0),
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addr = addrTable(resp_client_id),
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size = UInt(log2Up(csrDataBytes)))
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size = { require(false, "CSR MMIO ports no longer exist"); UInt(0) })
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io.mmio.w.valid := resp_wdata_pending
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io.mmio.w.bits := NastiWriteDataChannel(data = resp_status)
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io.mmio.b.ready := resp_wresp_pending
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@ -1,326 +0,0 @@
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// See LICENSE for license details.
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package uncore
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import Chisel._
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import Chisel.ImplicitConversions._
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import junctions._
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import junctions.NastiConstants._
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import cde.{Parameters, Field}
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case object HtifKey extends Field[HtifParameters]
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case class HtifParameters(width: Int, nCores: Int, offsetBits: Int, csrDataBits: Int, nSCR: Int = 64)
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trait HasHtifParameters {
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implicit val p: Parameters
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val htifExternal = p(HtifKey)
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val dataBits = p(TLKey(p(TLId))).dataBitsPerBeat
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val dataBeats = p(TLKey(p(TLId))).dataBeats
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val w = htifExternal.width
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val nSCR = htifExternal.nSCR
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val scrAddrBits = log2Up(nSCR)
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val scrDataBits = 64
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val scrDataBytes = scrDataBits / 8
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val csrDataBits = htifExternal.csrDataBits
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val csrDataBytes = csrDataBits / 8
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val offsetBits = htifExternal.offsetBits
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val nCores = htifExternal.nCores
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}
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abstract class HtifModule(implicit val p: Parameters) extends Module with HasHtifParameters
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abstract class HtifBundle(implicit val p: Parameters) extends ParameterizedBundle()(p)
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with HasHtifParameters
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class HostIO(w: Int) extends Bundle {
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val clk = Bool(OUTPUT)
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val clk_edge = Bool(OUTPUT)
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val in = Decoupled(Bits(width = w)).flip
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val out = Decoupled(Bits(width = w))
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override def cloneType = new HostIO(w).asInstanceOf[this.type]
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}
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class HtifIO(implicit p: Parameters) extends HtifBundle()(p) {
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val reset = Bool(INPUT)
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val id = UInt(INPUT, log2Up(nCores))
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val csr = new SmiIO(csrDataBits, 12).flip
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}
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class Htif(csr_RESET: Int)(implicit val p: Parameters) extends Module with HasHtifParameters {
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val io = new Bundle {
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val host = new HostIO(w)
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val cpu = Vec(nCores, new HtifIO).flip
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val mem = new ClientUncachedTileLinkIO
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val scr = new SmiIO(scrDataBits, scrAddrBits)
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}
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val short_request_bits = 64
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val long_request_bits = short_request_bits + dataBits*dataBeats
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require(short_request_bits % w == 0)
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val rx_count_w = 13 + log2Up(64) - log2Up(w) // data size field is 12 bits
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val rx_count = Reg(init=UInt(0,rx_count_w))
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val rx_shifter = Reg(Bits(width = short_request_bits))
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val rx_shifter_in = Cat(io.host.in.bits, rx_shifter(short_request_bits-1,w))
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val next_cmd = rx_shifter_in(3,0)
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val cmd = Reg(Bits())
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val size = Reg(Bits())
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val pos = Reg(Bits())
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val seqno = Reg(Bits())
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val addr = Reg(Bits())
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when (io.host.in.valid && io.host.in.ready) {
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rx_shifter := rx_shifter_in
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rx_count := rx_count + UInt(1)
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when (rx_count === UInt(short_request_bits/w-1)) {
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cmd := next_cmd
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size := rx_shifter_in(15,4)
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pos := rx_shifter_in(15,4+offsetBits-3)
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seqno := rx_shifter_in(23,16)
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addr := rx_shifter_in(63,24)
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}
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}
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val rx_word_count = (rx_count >> log2Up(short_request_bits/w))
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val rx_word_done = io.host.in.valid && rx_count(log2Up(short_request_bits/w)-1,0).andR
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val packet_ram_depth = long_request_bits/short_request_bits-1
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val packet_ram = Mem(packet_ram_depth, Bits(width = short_request_bits))
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when (rx_word_done && io.host.in.ready) {
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packet_ram(rx_word_count(log2Up(packet_ram_depth)-1,0) - UInt(1)) := rx_shifter_in
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}
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val cmd_readmem :: cmd_writemem :: cmd_readcr :: cmd_writecr :: cmd_ack :: cmd_nack :: Nil = Enum(UInt(), 6)
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val csr_addr = addr(io.cpu(0).csr.req.bits.addr.getWidth-1, 0)
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val csr_coreid = addr(log2Up(nCores)-1+20+1,20)
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val csr_wdata = packet_ram(0)
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val bad_mem_packet = size(offsetBits-1-3,0).orR || addr(offsetBits-1-3,0).orR
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val nack = Mux(cmd === cmd_readmem || cmd === cmd_writemem, bad_mem_packet,
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Mux(cmd === cmd_readcr || cmd === cmd_writecr, size =/= UInt(1),
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Bool(true)))
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val tx_count = Reg(init=UInt(0, rx_count_w))
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val tx_subword_count = tx_count(log2Up(short_request_bits/w)-1,0)
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val tx_word_count = tx_count(rx_count_w-1, log2Up(short_request_bits/w))
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val packet_ram_raddr = tx_word_count(log2Up(packet_ram_depth)-1,0) - UInt(1)
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when (io.host.out.valid && io.host.out.ready) {
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tx_count := tx_count + UInt(1)
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}
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val rx_done = rx_word_done && Mux(rx_word_count === UInt(0), next_cmd =/= cmd_writemem && next_cmd =/= cmd_writecr, rx_word_count === size || rx_word_count(log2Up(packet_ram_depth)-1,0) === UInt(0))
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val tx_size = Mux(!nack && (cmd === cmd_readmem || cmd === cmd_readcr || cmd === cmd_writecr), size, UInt(0))
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val tx_done = io.host.out.ready && tx_subword_count.andR && (tx_word_count === tx_size || tx_word_count > UInt(0) && packet_ram_raddr.andR)
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val state_rx :: state_csr_req :: state_csr_resp :: state_mem_rreq :: state_mem_wreq :: state_mem_rresp :: state_mem_wresp :: state_tx :: Nil = Enum(UInt(), 8)
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val state = Reg(init=state_rx)
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val (cnt, cnt_done) = Counter((state === state_mem_wreq && io.mem.acquire.ready) ||
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(state === state_mem_rresp && io.mem.grant.valid), dataBeats)
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val rx_cmd = Mux(rx_word_count === UInt(0), next_cmd, cmd)
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when (state === state_rx && rx_done) {
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state := Mux(rx_cmd === cmd_readmem, state_mem_rreq,
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Mux(rx_cmd === cmd_writemem, state_mem_wreq,
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Mux(rx_cmd === cmd_readcr || rx_cmd === cmd_writecr, state_csr_req,
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state_tx)))
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}
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when (state === state_mem_wreq) {
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when (cnt_done) { state := state_mem_wresp }
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}
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when (state === state_mem_rreq) {
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when(io.mem.acquire.ready) { state := state_mem_rresp }
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}
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when (state === state_mem_wresp && io.mem.grant.valid) {
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state := Mux(cmd === cmd_readmem || pos === UInt(1), state_tx, state_rx)
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pos := pos - UInt(1)
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addr := addr + UInt(1 << offsetBits-3)
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}
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when (state === state_mem_rresp && cnt_done) {
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state := Mux(cmd === cmd_readmem || pos === UInt(1), state_tx, state_rx)
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pos := pos - UInt(1)
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addr := addr + UInt(1 << offsetBits-3)
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}
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when (state === state_tx && tx_done) {
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when (tx_word_count === tx_size) {
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rx_count := UInt(0)
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tx_count := UInt(0)
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}
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state := Mux(cmd === cmd_readmem && pos =/= UInt(0), state_mem_rreq, state_rx)
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}
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val n = dataBits/short_request_bits
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val mem_req_data = (0 until n).map { i =>
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def addr(offset: UInt) =
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if (dataBits == short_request_bits) offset
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else Cat(offset, UInt(i, log2Up(n)))
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when (state === state_mem_rresp && io.mem.grant.valid) {
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packet_ram(addr(io.mem.grant.bits.addr_beat)) :=
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io.mem.grant.bits.data((i+1)*short_request_bits-1, i*short_request_bits)
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}
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packet_ram(addr(cnt))
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}.reverse.reduce(_##_)
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val init_addr = addr.toUInt >> (offsetBits-3)
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io.mem.acquire.valid := state === state_mem_rreq || state === state_mem_wreq
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io.mem.acquire.bits := Mux(cmd === cmd_writemem,
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PutBlock(
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addr_block = init_addr,
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addr_beat = cnt,
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client_xact_id = UInt(0),
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data = mem_req_data),
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GetBlock(addr_block = init_addr))
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io.mem.grant.ready := Bool(true)
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val csrReadData = Reg(Bits(width = io.cpu(0).csr.resp.bits.getWidth))
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for (i <- 0 until nCores) {
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val my_reset = Reg(init=Bool(true))
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val cpu = io.cpu(i)
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val me = csr_coreid === UInt(i)
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cpu.csr.req.valid := state === state_csr_req && me && csr_addr =/= UInt(csr_RESET)
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cpu.csr.req.bits.rw := cmd === cmd_writecr
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cpu.csr.req.bits.addr := csr_addr
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cpu.csr.req.bits.data := csr_wdata
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cpu.reset := my_reset
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when (cpu.csr.req.fire()) { state := state_csr_resp }
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when (state === state_csr_req && me && csr_addr === UInt(csr_RESET)) {
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when (cmd === cmd_writecr) {
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my_reset := csr_wdata(0)
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}
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csrReadData := my_reset.toBits
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state := state_tx
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}
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cpu.csr.resp.ready := Bool(true)
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when (state === state_csr_resp && cpu.csr.resp.valid) {
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csrReadData := cpu.csr.resp.bits
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state := state_tx
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}
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}
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io.scr.req.valid := (state === state_csr_req && csr_coreid.andR)
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io.scr.req.bits.addr := addr(scrAddrBits - 1, 0).toUInt
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io.scr.req.bits.data := csr_wdata
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io.scr.req.bits.rw := (cmd === cmd_writecr)
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io.scr.resp.ready := Bool(true)
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when (io.scr.req.fire()) { state := state_csr_resp }
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when (state === state_csr_resp && io.scr.resp.valid) {
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csrReadData := io.scr.resp.bits
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state := state_tx
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}
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val tx_cmd = Mux(nack, cmd_nack, cmd_ack)
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val tx_cmd_ext = Cat(Bits(0, 4-tx_cmd.getWidth), tx_cmd)
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val tx_header = Cat(addr, seqno, tx_size, tx_cmd_ext)
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val tx_data = Mux(tx_word_count === UInt(0), tx_header,
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Mux(cmd === cmd_readcr || cmd === cmd_writecr, csrReadData,
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packet_ram(packet_ram_raddr)))
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io.host.in.ready := state === state_rx
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io.host.out.valid := state === state_tx
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io.host.out.bits := tx_data >> Cat(tx_count(log2Up(short_request_bits/w)-1,0), Bits(0, log2Up(w)))
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}
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class NastiIOHostIOConverter(htifW: Int)(implicit val p: Parameters)
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extends Module with HasNastiParameters {
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val io = new Bundle {
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val nasti = (new NastiIO).flip
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val host = new HostIO(htifW).flip
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val reset = Bool(OUTPUT)
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}
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def cloneType = new NastiIOHostIOConverter(htifW).asInstanceOf[this.type]
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val raddr = io.nasti.ar.bits.addr(6, 2)
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val waddr = io.nasti.aw.bits.addr(6, 2)
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val DCOUNT_ADDR = 0x00
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val RFIFO_ADDR = 0x01
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val WFIFO_ADDR = 0x00
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val RESET_ADDR = 0x1f
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val FIFO_DEPTH = 32
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val fifo_ren = Reg(init = Bool(false))
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val fifo_wen = Reg(init = Bool(false))
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val fifo_rd_len = Reg(UInt(width = nastiXLenBits))
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val fifo_rd_id = Reg(UInt(width = nastiXIdBits))
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val fifo_wr_id = Reg(UInt(width = nastiXIdBits))
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val fifo_wr_ack = Reg(init = Bool(false))
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val rd_count = Reg(init = Bool(false))
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val wr_reset = Reg(init = Bool(false))
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when (io.nasti.ar.fire()) {
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fifo_rd_len := io.nasti.ar.bits.len
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fifo_rd_id := io.nasti.ar.bits.id
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when (raddr === UInt(RFIFO_ADDR)) {
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fifo_ren := Bool(true)
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} .elsewhen (raddr === UInt(DCOUNT_ADDR)) {
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rd_count := Bool(true)
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}
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}
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when (io.nasti.r.fire()) {
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when (io.nasti.r.bits.last) {
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fifo_ren := Bool(false)
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rd_count := Bool(false)
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} .otherwise { fifo_rd_len := fifo_rd_len - UInt(1) }
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}
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when (io.nasti.aw.fire()) {
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fifo_wr_id := io.nasti.aw.bits.id
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when (waddr === UInt(WFIFO_ADDR)) {
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fifo_wen := Bool(true)
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} .elsewhen (waddr === UInt(RESET_ADDR)) {
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wr_reset := Bool(true)
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}
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}
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when (io.nasti.w.fire() && io.nasti.w.bits.last) {
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fifo_wen := Bool(false)
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wr_reset := Bool(false)
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fifo_wr_ack := Bool(true)
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}
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when (io.nasti.b.fire()) { fifo_wr_ack := Bool(false) }
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io.nasti.ar.ready := !fifo_ren
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io.nasti.aw.ready := !fifo_wen && !fifo_wr_ack
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io.nasti.b.valid := fifo_wr_ack
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io.nasti.b.bits := NastiWriteResponseChannel(id = fifo_wr_id)
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io.reset := io.nasti.w.valid && wr_reset
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val hn_fifo = Module(new MultiWidthFifo(htifW, nastiXDataBits, FIFO_DEPTH))
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hn_fifo.io.in <> io.host.out
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hn_fifo.io.out.ready := fifo_ren && io.nasti.r.ready
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io.nasti.r.valid := (fifo_ren && hn_fifo.io.out.valid) || rd_count
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io.nasti.r.bits := NastiReadDataChannel(
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id = fifo_rd_id,
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data = Mux(fifo_ren, hn_fifo.io.out.bits, hn_fifo.io.count),
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last = (fifo_rd_len === UInt(0)))
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val nh_fifo = Module(new MultiWidthFifo(nastiXDataBits, htifW, FIFO_DEPTH))
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io.host.in <> nh_fifo.io.out
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nh_fifo.io.in.valid := fifo_wen && io.nasti.w.valid
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nh_fifo.io.in.bits := io.nasti.w.bits.data
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io.nasti.w.ready := (fifo_wen && nh_fifo.io.in.ready) || wr_reset
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assert(!io.nasti.w.valid || io.nasti.w.bits.strb.andR,
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"Nasti to HostIO converter cannot take partial writes")
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assert(!io.nasti.ar.valid ||
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io.nasti.ar.bits.len === UInt(0) ||
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io.nasti.ar.bits.burst === BURST_FIXED,
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"Nasti to HostIO converter can only take fixed bursts")
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assert(!io.nasti.aw.valid ||
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io.nasti.aw.bits.len === UInt(0) ||
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io.nasti.aw.bits.burst === BURST_FIXED,
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"Nasti to HostIO converter can only take fixed bursts")
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}
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@ -1,102 +0,0 @@
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package uncore
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import Chisel._
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import junctions.SmiIO
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import cde.Parameters
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import scala.collection.mutable.HashMap
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import scala.collection.mutable.ArrayBuffer
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/** Stores a map between SCR file names and address in the SCR file, which can
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* later be dumped to a header file for the test bench. */
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class SCRFileMap(prefix: String, maxAddress: Int, baseAddress: BigInt) {
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private val addr2name = HashMap.empty[Int, String]
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private val name2addr = HashMap.empty[String, Int]
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def allocate(address: Int, name: String): Int = {
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Predef.assert(!addr2name.contains(address), "address already allocated")
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Predef.assert(!name2addr.contains(name), "name already allocated")
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Predef.assert(address < maxAddress, "address too large")
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addr2name += (address -> name)
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name2addr += (name -> address)
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println(prefix + ": %x -> ".format(baseAddress + address) + name)
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address
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}
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def allocate(name: String): Int = {
|
||||
val addr = (0 until maxAddress).filter{ addr => !addr2name.contains(addr) }(0)
|
||||
allocate(addr, name)
|
||||
}
|
||||
|
||||
def as_c_header(): String = {
|
||||
addr2name.map{ case(address, name) =>
|
||||
List(
|
||||
"#define " + prefix + "__" + name + "__PADDR 0x%x".format(baseAddress + address),
|
||||
"#define " + prefix + "__" + name + "__OFFSET 0x%x".format(address)
|
||||
)
|
||||
}.flatten.mkString("\n") + "\n"
|
||||
}
|
||||
}
|
||||
|
||||
class SCRIO(map: SCRFileMap)(implicit p: Parameters) extends HtifBundle()(p) {
|
||||
val rdata = Vec(nSCR, Bits(INPUT, scrDataBits))
|
||||
val wen = Bool(OUTPUT)
|
||||
val waddr = UInt(OUTPUT, log2Up(nSCR))
|
||||
val wdata = Bits(OUTPUT, scrDataBits)
|
||||
|
||||
def attach(regs: Seq[Data], name_base: String): Seq[Data] = {
|
||||
regs.zipWithIndex.map{ case(reg, i) => attach(reg, name_base + "__" + i) }
|
||||
}
|
||||
|
||||
def attach(reg: Data, name: String): Data = {
|
||||
val addr = map.allocate(name)
|
||||
when (wen && (waddr === UInt(addr))) {
|
||||
reg := wdata
|
||||
}
|
||||
rdata(addr) := reg
|
||||
reg
|
||||
}
|
||||
|
||||
def allocate(address: Int, name: String): Unit = {
|
||||
map.allocate(address, name)
|
||||
}
|
||||
}
|
||||
|
||||
class SCRFile(prefix: String, baseAddress: BigInt)(implicit p: Parameters) extends HtifModule()(p) {
|
||||
val map = new SCRFileMap(prefix, 64, baseAddress)
|
||||
AllSCRFiles += map
|
||||
|
||||
val io = new Bundle {
|
||||
val smi = new SmiIO(scrDataBits, scrAddrBits).flip
|
||||
val scr = new SCRIO(map)
|
||||
}
|
||||
|
||||
val scr_rdata = Wire(Vec(io.scr.rdata.size, Bits(width=scrDataBits)))
|
||||
for (i <- 0 until scr_rdata.size)
|
||||
scr_rdata(i) := io.scr.rdata(i)
|
||||
|
||||
val read_addr = Reg(init = UInt(0, scrAddrBits))
|
||||
val resp_valid = Reg(init = Bool(false))
|
||||
|
||||
io.smi.req.ready := !resp_valid
|
||||
io.smi.resp.valid := resp_valid
|
||||
io.smi.resp.bits := scr_rdata(read_addr)
|
||||
|
||||
io.scr.wen := io.smi.req.fire() && io.smi.req.bits.rw
|
||||
io.scr.wdata := io.smi.req.bits.data
|
||||
io.scr.waddr := io.smi.req.bits.addr
|
||||
|
||||
when (io.smi.req.fire()) {
|
||||
read_addr := io.smi.req.bits.addr
|
||||
resp_valid := Bool(true)
|
||||
}
|
||||
when (io.smi.resp.fire()) { resp_valid := Bool(false) }
|
||||
}
|
||||
|
||||
/** Every elaborated SCR file ends up in this global arry so it can be printed
|
||||
* out later. */
|
||||
object AllSCRFiles {
|
||||
private var maps = ArrayBuffer.empty[SCRFileMap]
|
||||
|
||||
def +=(map: SCRFileMap): Unit = { maps += map }
|
||||
def foreach( f: (SCRFileMap => Unit) ): Unit = { maps.foreach{ m => f(m) } }
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user