riscv/rocket-chip
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update to new Mem style

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This commit is contained in:
Andrew Waterman 2013-02-20 16:09:46 -08:00
parent 9f89c812b7
commit 35349d227f
2 changed files with 10 additions and 19 deletions
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12
rocket/src/main/scala/icache.scala
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@ -177,7 +177,7 @@ class ICache(implicit c: ICacheConfig, lnconf: LogicalNetworkConfiguration) exte
val enc_tagbits = c.code.width(c.tagbits) val enc_tagbits = c.code.width(c.tagbits)
val tag_array = Mem(c.sets, seqRead = true) { Bits(width = enc_tagbits*c.assoc) } val tag_array = Mem(c.sets, seqRead = true) { Bits(width = enc_tagbits*c.assoc) }
val tag_rdata = Reg() { Bits() } val tag_raddr = Reg{UFix()}
when (refill_done) { when (refill_done) {
val wmask = FillInterleaved(enc_tagbits, if (c.dm) Bits(1) else UFixToOH(repl_way)) val wmask = FillInterleaved(enc_tagbits, if (c.dm) Bits(1) else UFixToOH(repl_way))
val tag = c.code.encode(s2_tag) val tag = c.code.encode(s2_tag)
@ -185,7 +185,7 @@ class ICache(implicit c: ICacheConfig, lnconf: LogicalNetworkConfiguration) exte
} }
// /*.else*/when (s0_valid) { // uncomment ".else" to infer 6T SRAM // /*.else*/when (s0_valid) { // uncomment ".else" to infer 6T SRAM
.elsewhen (s0_valid) { .elsewhen (s0_valid) {
tag_rdata := tag_array(s0_pgoff(c.untagbits-1,c.offbits)) tag_raddr := s0_pgoff(c.untagbits-1,c.offbits)
} }
val vb_array = Reg(resetVal = Bits(0, c.lines)) val vb_array = Reg(resetVal = Bits(0, c.lines))
@ -209,7 +209,7 @@ class ICache(implicit c: ICacheConfig, lnconf: LogicalNetworkConfiguration) exte
val s2_vb = Reg() { Bool() } val s2_vb = Reg() { Bool() }
val s2_tag_disparity = Reg() { Bool() } val s2_tag_disparity = Reg() { Bool() }
val s2_tag_match = Reg() { Bool() } val s2_tag_match = Reg() { Bool() }
val tag_out = tag_rdata(enc_tagbits*(i+1)-1, enc_tagbits*i) val tag_out = tag_array(tag_raddr)(enc_tagbits*(i+1)-1, enc_tagbits*i)
when (s1_valid && rdy && !stall) { when (s1_valid && rdy && !stall) {
s2_vb := s1_vb s2_vb := s1_vb
s2_tag_disparity := c.code.decode(tag_out).error s2_tag_disparity := c.code.decode(tag_out).error
@ -223,17 +223,17 @@ class ICache(implicit c: ICacheConfig, lnconf: LogicalNetworkConfiguration) exte
for (i <- 0 until c.assoc) { for (i <- 0 until c.assoc) {
val data_array = Mem(c.sets*REFILL_CYCLES, seqRead = true){ Bits(width = c.code.width(c.databits)) } val data_array = Mem(c.sets*REFILL_CYCLES, seqRead = true){ Bits(width = c.code.width(c.databits)) }
val s1_dout = Reg(){ Bits() } val s1_raddr = Reg{UFix()}
when (io.mem.grant.valid && repl_way === UFix(i)) { when (io.mem.grant.valid && repl_way === UFix(i)) {
val d = io.mem.grant.bits.payload.data val d = io.mem.grant.bits.payload.data
data_array(Cat(s2_idx,rf_cnt)) := c.code.encode(d) data_array(Cat(s2_idx,rf_cnt)) := c.code.encode(d)
} }
// /*.else*/when (s0_valid) { // uncomment ".else" to infer 6T SRAM // /*.else*/when (s0_valid) { // uncomment ".else" to infer 6T SRAM
.elsewhen (s0_valid) { .elsewhen (s0_valid) {
s1_dout := data_array(s0_pgoff(c.untagbits-1,c.offbits-rf_cnt.getWidth)) s1_raddr := s0_pgoff(c.untagbits-1,c.offbits-rf_cnt.getWidth)
} }
// if s1_tag_match is critical, replace with partial tag check // if s1_tag_match is critical, replace with partial tag check
when (s1_valid && rdy && !stall && (Bool(c.dm) || s1_tag_match(i))) { s2_dout(i) := s1_dout } when (s1_valid && rdy && !stall && (Bool(c.dm) || s1_tag_match(i))) { s2_dout(i) := data_array(s1_raddr) }
} }
val s2_dout_word = s2_dout.map(x => (x >> (s2_offset(log2Up(c.databits/8)-1,log2Up(c.ibytes)) << log2Up(c.ibytes*8)))(c.ibytes*8-1,0)) val s2_dout_word = s2_dout.map(x => (x >> (s2_offset(log2Up(c.databits/8)-1,log2Up(c.ibytes)) << log2Up(c.ibytes*8)))(c.ibytes*8-1,0))
io.resp.bits.data := Mux1H(s2_tag_hit, s2_dout_word) io.resp.bits.data := Mux1H(s2_tag_hit, s2_dout_word)

17
rocket/src/main/scala/nbdcache.scala
View File

@ -583,7 +583,6 @@ class MetaDataArray(implicit conf: DCacheConfig) extends Component {
val metabits = io.write.bits.data.state.width + conf.tagbits val metabits = io.write.bits.data.state.width + conf.tagbits
val tags = Mem(conf.sets, seqRead = true) { UFix(width = metabits*conf.ways) } val tags = Mem(conf.sets, seqRead = true) { UFix(width = metabits*conf.ways) }
val tag = Reg{UFix()}
when (rst || io.write.valid) { when (rst || io.write.valid) {
val addr = Mux(rst, rst_cnt, io.write.bits.idx) val addr = Mux(rst, rst_cnt, io.write.bits.idx)
@ -591,9 +590,7 @@ class MetaDataArray(implicit conf: DCacheConfig) extends Component {
val mask = Mux(rst, Fix(-1), io.write.bits.way_en) val mask = Mux(rst, Fix(-1), io.write.bits.way_en)
tags.write(addr, Fill(conf.ways, data), FillInterleaved(metabits, mask)) tags.write(addr, Fill(conf.ways, data), FillInterleaved(metabits, mask))
} }
when (io.read.valid) { val tag = tags(RegEn(io.read.bits.addr >> conf.offbits, io.read.valid))
tag := tags(io.read.bits.addr(conf.untagbits-1,conf.offbits))
}
for (w <- 0 until conf.ways) { for (w <- 0 until conf.ways) {
val m = tag(metabits*(w+1)-1, metabits*w) val m = tag(metabits*(w+1)-1, metabits*w)
@ -619,7 +616,7 @@ class DataArray(implicit conf: DCacheConfig) extends Component {
for (w <- 0 until conf.ways by conf.wordsperrow) { for (w <- 0 until conf.ways by conf.wordsperrow) {
val wway_en = io.write.bits.way_en(w+conf.wordsperrow-1,w) val wway_en = io.write.bits.way_en(w+conf.wordsperrow-1,w)
val rway_en = io.read.bits.way_en(w+conf.wordsperrow-1,w) val rway_en = io.read.bits.way_en(w+conf.wordsperrow-1,w)
val resp = Vec(conf.wordsperrow){Reg{Bits(width = conf.bitsperrow)}} val resp = Vec(conf.wordsperrow){Bits(width = conf.bitsperrow)}
val r_raddr = RegEn(io.read.bits.addr, io.read.valid) val r_raddr = RegEn(io.read.bits.addr, io.read.valid)
for (p <- 0 until resp.size) { for (p <- 0 until resp.size) {
val array = Mem(conf.sets*REFILL_CYCLES, seqRead = true){ Bits(width=conf.bitsperrow) } val array = Mem(conf.sets*REFILL_CYCLES, seqRead = true){ Bits(width=conf.bitsperrow) }
@ -628,9 +625,7 @@ class DataArray(implicit conf: DCacheConfig) extends Component {
val mask = FillInterleaved(conf.encdatabits, wway_en) val mask = FillInterleaved(conf.encdatabits, wway_en)
array.write(waddr, data, mask) array.write(waddr, data, mask)
} }
when (rway_en.orR && io.read.valid) { resp(p) := array(RegEn(raddr, rway_en.orR && io.read.valid))
resp(p) := array(raddr)
}
} }
for (dw <- 0 until conf.wordsperrow) { for (dw <- 0 until conf.wordsperrow) {
val r = AVec(resp.map(_(conf.encdatabits*(dw+1)-1,conf.encdatabits*dw))) val r = AVec(resp.map(_(conf.encdatabits*(dw+1)-1,conf.encdatabits*dw)))
@ -643,15 +638,11 @@ class DataArray(implicit conf: DCacheConfig) extends Component {
} else { } else {
val wmask = FillInterleaved(conf.encdatabits, io.write.bits.wmask) val wmask = FillInterleaved(conf.encdatabits, io.write.bits.wmask)
for (w <- 0 until conf.ways) { for (w <- 0 until conf.ways) {
val rdata = Reg() { Bits() }
val array = Mem(conf.sets*REFILL_CYCLES, seqRead = true){ Bits(width=conf.bitsperrow) } val array = Mem(conf.sets*REFILL_CYCLES, seqRead = true){ Bits(width=conf.bitsperrow) }
when (io.write.bits.way_en(w) && io.write.valid) { when (io.write.bits.way_en(w) && io.write.valid) {
array.write(waddr, io.write.bits.data, wmask) array.write(waddr, io.write.bits.data, wmask)
} }
when (io.read.bits.way_en(w) && io.read.valid) { io.resp(w) := array(RegEn(raddr, io.read.bits.way_en(w) && io.read.valid))
rdata := array(raddr)
}
io.resp(w) := rdata
} }
} }