riscv/rocket-chip
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clock gate X/M and M/W store data registers

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This commit is contained in:
Andrew Waterman
2012-11-26 20:33:41 -08:00
parent 8a6ff5f9aa
commit 352bb464b5
2 changed files with 22 additions and 10 deletions
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4
rocket/src/main/scala/ctrl.scala
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@@ -35,6 +35,8 @@ class ioCtrlDpath extends Bundle()
val wb_wen = Bool(OUTPUT);
val wb_valid = Bool(OUTPUT)
val ex_mem_type = Bits(OUTPUT, 3)
val ex_rs2_val = Bool(OUTPUT)
val mem_rs2_val = Bool(OUTPUT)
// exception handling
val exception = Bool(OUTPUT);
val cause = UFix(OUTPUT, 6);
@@ -746,6 +748,8 @@ class Control(implicit conf: RocketConfiguration) extends Component
io.dpath.eret := wb_reg_eret
io.dpath.ex_mem_type := ex_reg_mem_type
io.dpath.ex_br_type := ex_reg_br_type
io.dpath.ex_rs2_val := ex_reg_mem_val && isWrite(ex_reg_mem_cmd) || ex_reg_vec_val
io.dpath.mem_rs2_val := mem_reg_vec_val
io.fpu.valid := !ctrl_killd && id_fp_val
io.fpu.killx := ctrl_killx