From ad0b9a0b1bfd5623f37d83935198eb8c57a22dd7 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Fri, 5 Jan 2018 13:58:14 -0800 Subject: [PATCH 1/2] Reduce cases in which FENCE.I must flush D$ Memory regions that are uncacheable or have get/put effects should not reside in the D$, so there is no need to flush them. --- src/main/scala/rocket/DCache.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/rocket/DCache.scala b/src/main/scala/rocket/DCache.scala index e3982151..9eea5875 100644 --- a/src/main/scala/rocket/DCache.scala +++ b/src/main/scala/rocket/DCache.scala @@ -722,7 +722,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) { metaArb.io.in(5).bits.data := metaArb.io.in(4).bits.data // Only flush D$ on FENCE.I if some cached executable regions are untracked. - val supports_flush = !edge.manager.managers.forall(m => !m.supportsAcquireT || !m.executable || m.regionType >= RegionType.TRACKED) + val supports_flush = !edge.manager.managers.forall(m => !m.supportsAcquireT || !m.executable || m.regionType >= RegionType.TRACKED || m.regionType <= RegionType.UNCACHEABLE) if (supports_flush) { when (tl_out_a.fire() && !s2_uncached) { flushed := false } when (flushing) { From 000cde2f8aa9bee7773cb155c27476a76c50d1c3 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Fri, 5 Jan 2018 14:00:42 -0800 Subject: [PATCH 2/2] Make ErrorDevice UNCACHEABLE instead of UNCACHED ...even though it still supports Acquire. This avoids needing to flush the D$ on FENCE.I because of the presence of the ErrorDevice. --- src/main/scala/devices/tilelink/Error.scala | 2 +- src/main/scala/tilelink/Parameters.scala | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/scala/devices/tilelink/Error.scala b/src/main/scala/devices/tilelink/Error.scala index d9df000c..89c099df 100644 --- a/src/main/scala/devices/tilelink/Error.scala +++ b/src/main/scala/devices/tilelink/Error.scala @@ -26,7 +26,7 @@ abstract class DevNullDevice(params: ErrorParams, beatBytes: Int = 4) Seq(TLManagerParameters( address = params.address, resources = device.reg("mem"), - regionType = RegionType.UNCACHED, + regionType = RegionType.UNCACHEABLE, executable = true, supportsAcquireT = xfer, supportsAcquireB = xfer, diff --git a/src/main/scala/tilelink/Parameters.scala b/src/main/scala/tilelink/Parameters.scala index 3ab22ee1..d6dcd257 100644 --- a/src/main/scala/tilelink/Parameters.scala +++ b/src/main/scala/tilelink/Parameters.scala @@ -40,7 +40,7 @@ case class TLManagerParameters( require (supportsAcquireB.contains(supportsAcquireT), s"AcquireB($supportsAcquireB) < AcquireT($supportsAcquireT)") // Make sure that the regionType agrees with the capabilities - require (!supportsAcquireB || regionType >= RegionType.UNCACHED) // acquire -> uncached, tracked, cached + require (!supportsAcquireB || regionType >= RegionType.UNCACHEABLE) // acquire -> uncached, tracked, cached require (regionType <= RegionType.UNCACHED || supportsAcquireB) // tracked, cached -> acquire require (regionType != RegionType.UNCACHED || supportsGet) // uncached -> supportsGet