riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Revert "Avoid data corruption under correctable tag error during flush (#1130)"

Browse Source 
This reverts commit 44eb4d12b5.
This commit is contained in:
Andrew Waterman
2017-11-29 16:09:30 -08:00
parent 44eb4d12b5
commit 34d86ef665
1 changed files with 2 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
src/main/scala/rocket/DCache.scala
View File

@@ -242,8 +242,8 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
}
val s2_probe_way = RegEnable(s1_hit_way, s1_probe)
val s2_probe_state = RegEnable(s1_hit_state, s1_probe)
val s2_hit_way = RegEnable(s1_hit_way, s1_valid_not_nacked || s1_flush_valid)
val s2_hit_state = RegEnable(s1_hit_state, s1_valid_not_nacked || s1_flush_valid)
val s2_hit_way = RegEnable(s1_hit_way, s1_valid_not_nacked)
val s2_hit_state = RegEnable(s1_hit_state, s1_valid_not_nacked)
val s2_waw_hazard = RegEnable(s1_waw_hazard, s1_valid_not_nacked)
val s2_store_merge = Wire(Bool())
val s2_hit_valid = s2_hit_state.isValid()