diff --git a/uncore/src/coherence.scala b/uncore/src/coherence.scala
index 1fa09fe6..d97cc2da 100644
--- a/uncore/src/coherence.scala
+++ b/uncore/src/coherence.scala
@@ -121,8 +121,7 @@ class ThreeStateIncoherence extends IncoherentPolicy {
   def isVoluntary(gnt: Grant) = gnt.g_type === grantVoluntaryAck
 
   def getAcquireTypeOnPrimaryMiss(cmd: Bits, state: UFix): UFix = {
-    val (read, write) = cpuCmdToRW(cmd)
-    Mux(write || cmd === M_PFW, acquireReadDirty, acquireReadClean)
+    Mux(isWriteIntent(cmd), acquireReadDirty, acquireReadClean)
   }
   def getAcquireTypeOnSecondaryMiss(cmd: Bits, state: UFix, outstanding: Acquire): UFix = {
     val (read, write) = cpuCmdToRW(cmd)
@@ -517,8 +516,7 @@ class MSICoherence extends CoherencePolicyWithUncached {
   def isVoluntary(gnt: Grant) = gnt.g_type === grantVoluntaryAck
 
   def getAcquireTypeOnPrimaryMiss(cmd: Bits, state: UFix): UFix = {
-    val (read, write) = cpuCmdToRW(cmd)
-    Mux(write || cmd === M_PFW, acquireReadExclusive, acquireReadShared)
+    Mux(isWriteIntent(cmd), acquireReadExclusive, acquireReadShared)
   }
   def getAcquireTypeOnSecondaryMiss(cmd: Bits, state: UFix, outstanding: Acquire): UFix = {
     val (read, write) = cpuCmdToRW(cmd)
@@ -679,8 +677,7 @@ class MESICoherence extends CoherencePolicyWithUncached {
   def isVoluntary(gnt: Grant) = gnt.g_type === grantVoluntaryAck
 
   def getAcquireTypeOnPrimaryMiss(cmd: Bits, state: UFix): UFix = {
-    val (read, write) = cpuCmdToRW(cmd)
-    Mux(write || cmd === M_PFW, acquireReadExclusive, acquireReadShared)
+    Mux(isWriteIntent(cmd), acquireReadExclusive, acquireReadShared)
   }
   def getAcquireTypeOnSecondaryMiss(cmd: Bits, state: UFix, outstanding: Acquire): UFix = {
     val (read, write) = cpuCmdToRW(cmd)
@@ -857,8 +854,7 @@ class MigratoryCoherence extends CoherencePolicyWithUncached {
   def isVoluntary(gnt: Grant) = gnt.g_type === grantVoluntaryAck
 
   def getAcquireTypeOnPrimaryMiss(cmd: Bits, state: UFix): UFix = {
-    val (read, write) = cpuCmdToRW(cmd)
-    Mux(write || cmd === M_PFW, Mux(state === tileInvalid, acquireReadExclusive, acquireInvalidateOthers), acquireReadShared)
+    Mux(isWriteIntent(cmd), Mux(state === tileInvalid, acquireReadExclusive, acquireInvalidateOthers), acquireReadShared)
   }
   def getAcquireTypeOnSecondaryMiss(cmd: Bits, state: UFix, outstanding: Acquire): UFix = {
     val (read, write) = cpuCmdToRW(cmd)
diff --git a/uncore/src/consts.scala b/uncore/src/consts.scala
index d348e0ff..cde8d3b9 100644
--- a/uncore/src/consts.scala
+++ b/uncore/src/consts.scala
@@ -45,27 +45,31 @@ trait MemoryOpConstants {
   val MT_HU = Bits("b101", 3);
   val MT_WU = Bits("b110", 3);
 
-  val M_X       = Bits("b????", 4);
-  val M_XRD     = Bits("b0000", 4); // int load
-  val M_XWR     = Bits("b0001", 4); // int store
-  val M_PFR     = Bits("b0010", 4); // prefetch with intent to read
-  val M_PFW     = Bits("b0011", 4); // prefetch with intent to write
-  val M_FENCE   = Bits("b0101", 4); // memory fence
-  val M_INV     = Bits("b0110", 4); // write back and invalidate line
-  val M_CLN     = Bits("b0111", 4); // write back line
-  val M_XA_ADD  = Bits("b1000", 4);
-  val M_XA_SWAP = Bits("b1001", 4);
-  val M_XA_AND  = Bits("b1010", 4);
-  val M_XA_OR   = Bits("b1011", 4);
-  val M_XA_MIN  = Bits("b1100", 4);
-  val M_XA_MAX  = Bits("b1101", 4);
-  val M_XA_MINU = Bits("b1110", 4);
-  val M_XA_MAXU = Bits("b1111", 4);
+  val M_SZ      = 5
+  val M_X       = Bits("b?????");
+  val M_XRD     = Bits("b00000"); // int load
+  val M_XWR     = Bits("b00001"); // int store
+  val M_PFR     = Bits("b00010"); // prefetch with intent to read
+  val M_PFW     = Bits("b00011"); // prefetch with intent to write
+  val M_FENCE   = Bits("b00101"); // memory fence
+  val M_XLR     = Bits("b00110");
+  val M_XSC     = Bits("b00111");
+  val M_XA_ADD  = Bits("b01000");
+  val M_XA_SWAP = Bits("b01001");
+  val M_XA_AND  = Bits("b01010");
+  val M_XA_OR   = Bits("b01011");
+  val M_XA_MIN  = Bits("b01100");
+  val M_XA_MAX  = Bits("b01101");
+  val M_XA_MINU = Bits("b01110");
+  val M_XA_MAXU = Bits("b01111");
+  val M_INV     = Bits("b10000"); // write back and invalidate line
+  val M_CLN     = Bits("b10001"); // write back line
 
   def isAMO(cmd: Bits) = cmd(3)
   def isPrefetch(cmd: Bits) = cmd === M_PFR || cmd === M_PFW
-  def isRead(cmd: Bits) = cmd === M_XRD || isAMO(cmd)
-  def isWrite(cmd: Bits) = cmd === M_XWR || isAMO(cmd)
+  def isRead(cmd: Bits) = cmd === M_XRD || cmd === M_XLR || isAMO(cmd)
+  def isWrite(cmd: Bits) = cmd === M_XWR || cmd === M_XSC || isAMO(cmd)
+  def isWriteIntent(cmd: Bits) = isWrite(cmd) || cmd === M_PFW || cmd === M_XLR
 }
 
 trait MemoryInterfaceConstants extends