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don't synthesize vsim verilog in Travis

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Howard Mao 2016-08-09 18:24:59 -07:00
parent 405294167f
commit 33d5905c50
1 changed files with 0 additions and 1 deletions
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.travis.yml
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@ -46,7 +46,6 @@ before_install:
- export CXX=g++-4.8 CC=gcc-4.8 - export CXX=g++-4.8 CC=gcc-4.8
script: script:
- make vsim-verilog -C regression SUITE=$SUITE TORTURE_CONFIG=default CHISEL_VERSION=$CHISEL_VERSION
- make emulator-ndebug -C regression SUITE=$SUITE TORTURE_CONFIG=default CHISEL_VERSION=$CHISEL_VERSION - make emulator-ndebug -C regression SUITE=$SUITE TORTURE_CONFIG=default CHISEL_VERSION=$CHISEL_VERSION
- make emulator-regression-tests -C regression SUITE=$SUITE TORTURE_CONFIG=default CHISEL_VERSION=$CHISEL_VERSION - make emulator-regression-tests -C regression SUITE=$SUITE TORTURE_CONFIG=default CHISEL_VERSION=$CHISEL_VERSION