riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Fix haltnot reporting (previously always returned 0)

Browse Source
This commit is contained in:
Andrew Waterman 2017-03-09 12:37:20 -08:00
parent 24a2278fc4
commit 33b6d48376
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/main/scala/uncore/devices/Debug.scala
View File

@ -724,7 +724,7 @@ trait DebugModule extends Module with HasDebugModuleParameters with HasRegMap {
// This logic assumes only up to 128 components. // This logic assumes only up to 128 components.
rdHaltnotStatus := Bits(0) rdHaltnotStatus := Bits(0)
for (ii <- 0 until numHaltnotStatus) { for (ii <- 0 until numHaltnotStatus) {
when (dbReq.addr === UInt(ii)) { when (dbReq.addr(1, 0) === UInt(ii)) {
rdHaltnotStatus := haltnotStatus(ii) rdHaltnotStatus := haltnotStatus(ii)
} }
} }