riscv/rocket-chip
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fix more Chisel3 deprecations

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This commit is contained in:
Howard Mao 2016-01-14 15:06:30 -08:00
parent fc638c6339
commit 33aa64212d
6 changed files with 12 additions and 12 deletions
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2
junctions

@ -1 +1 @@
Subproject commit b4c81b6ea5f3f4297469ccff3bd979695630bf92 Subproject commit 28fb71e3d7d0903dc2064d8e9494d7ca0c9529e2

2
rocket

@ -1 +1 @@
Subproject commit 976b5c3425b211170cf199206b0ff5c1876d0cdf Subproject commit 8d8c2a8884fcf8680834189a5b6ebda1cff4b7cc

4
src/main/scala/Network.scala
View File

@ -35,8 +35,8 @@ abstract class RocketChipNetwork(
val nClients = tlNClients val nClients = tlNClients
val nManagers = tlNManagers val nManagers = tlNManagers
val io = new Bundle { val io = new Bundle {
val clients = Vec(new ClientTileLinkIO, nClients).flip val clients = Vec(nClients, new ClientTileLinkIO).flip
val managers = Vec(new ManagerTileLinkIO, nManagers).flip val managers = Vec(nManagers, new ManagerTileLinkIO).flip
} }
val clients = io.clients.zipWithIndex.map { val clients = io.clients.zipWithIndex.map {

12
src/main/scala/RocketChip.scala
View File

@ -76,7 +76,7 @@ class BasicTopIO(implicit val p: Parameters) extends ParameterizedBundle()(p)
} }
class TopIO(implicit p: Parameters) extends BasicTopIO()(p) { class TopIO(implicit p: Parameters) extends BasicTopIO()(p) {
val mem = Vec(new NastiIO, nMemChannels) val mem = Vec(nMemChannels, new NastiIO)
} }
object TopUtils { object TopUtils {
@ -140,10 +140,10 @@ class Uncore(implicit val p: Parameters) extends Module
with HasTopLevelParameters { with HasTopLevelParameters {
val io = new Bundle { val io = new Bundle {
val host = new HostIO(htifW) val host = new HostIO(htifW)
val mem = Vec(new NastiIO, nMemChannels) val mem = Vec(nMemChannels, new NastiIO)
val tiles_cached = Vec(nCachedTilePorts, new ClientTileLinkIO).flip val tiles_cached = Vec(nCachedTilePorts, new ClientTileLinkIO).flip
val tiles_uncached = Vec(nUncachedTilePorts, new ClientUncachedTileLinkIO).flip val tiles_uncached = Vec(nUncachedTilePorts, new ClientUncachedTileLinkIO).flip
val htif = Vec(new HtifIO, nTiles).flip val htif = Vec(nTiles, new HtifIO).flip
val mem_backup_ctrl = new MemBackupCtrlIO val mem_backup_ctrl = new MemBackupCtrlIO
val mmio = new NastiIO val mmio = new NastiIO
val dma = Vec(nTiles, new DmaIO).flip val dma = Vec(nTiles, new DmaIO).flip
@ -205,11 +205,11 @@ class OuterMemorySystem(implicit val p: Parameters) extends Module with HasTopLe
val tiles_cached = Vec(nCachedTilePorts, new ClientTileLinkIO).flip val tiles_cached = Vec(nCachedTilePorts, new ClientTileLinkIO).flip
val tiles_uncached = Vec(nUncachedTilePorts, new ClientUncachedTileLinkIO).flip val tiles_uncached = Vec(nUncachedTilePorts, new ClientUncachedTileLinkIO).flip
val htif_uncached = (new ClientUncachedTileLinkIO).flip val htif_uncached = (new ClientUncachedTileLinkIO).flip
val incoherent = Vec(Bool(), nTiles).asInput val incoherent = Vec(nTiles, Bool()).asInput
val mem = Vec(new NastiIO, nMemChannels) val mem = Vec(nMemChannels, new NastiIO)
val mem_backup = new MemSerializedIO(htifW) val mem_backup = new MemSerializedIO(htifW)
val mem_backup_en = Bool(INPUT) val mem_backup_en = Bool(INPUT)
val csr = Vec(new SmiIO(xLen, csrAddrBits), nTiles) val csr = Vec(nTiles, new SmiIO(xLen, csrAddrBits))
val scr = new SmiIO(xLen, scrAddrBits) val scr = new SmiIO(xLen, scrAddrBits)
val mmio = new NastiIO val mmio = new NastiIO
val deviceTree = new NastiIO val deviceTree = new NastiIO

2
uncore

@ -1 +1 @@
Subproject commit 73df652b7f92c553dcc3732761b947896f48cfe9 Subproject commit 98fd46ef38adb93bf60d3e08eaabed33e918cc89

2
zscale

@ -1 +1 @@
Subproject commit a6ce530a3dc42eed1ada4b0d7fffe5f6a3cc5d08 Subproject commit de370f6baa03ba47f9a39b31a36336e805047955