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tilelink2 RAMModel: fix put, get, putAck, getAck case (#282)

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This case should result in undefined data for the Get.
It was previously requiring the Get to return the new Put data,
which is only guaranteed by a FIFO device.
This commit is contained in:
Wesley W. Terpstra
2016-09-13 15:44:36 -07:00
committed by GitHub
parent 28982ab569
commit 33a05786db
2 changed files with 62 additions and 13 deletions
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4
src/main/scala/uncore/tilelink2/Parameters.scala
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@ -179,6 +179,10 @@ case class TLManagerPortParameters(managers: Seq[TLManagerParameters], beatBytes
def findById(id: UInt) = Vec(managers.map(_.sinkId.contains(id)))
def findId(address: UInt) = Mux1H(find(address), managers.map(m => UInt(m.sinkId.start)))
// Note: returns the actual fifoId + 1 or 0 if None
def findFifoId(address: UInt) = Mux1H(find(address), managers.map(m => UInt(m.fifoId.map(_+1).getOrElse(0))))
def hasFifoId(address: UInt) = Mux1H(find(address), managers.map(m => Bool(m.fifoId.isDefined)))
// !!! need a cheaper version of find, where we assume a valid address match exists
// Does this Port manage this ID/address?