refactor vector control logic & datapath in the rocket core

rocket/src/main/scala/cpu.scala

@@ -130,8 +130,11 @@ class rocketProc extends Component
 
   if (HAVE_VEC)
   {
+    dpath.io.vec_ctrl <> ctrl.io.vec_dpath
+
     val vu = new vu()
 
+    // hooking up vector I$
     vitlb.io.cpu.invalidate := dpath.io.ptbr_wen
     vitlb.io.cpu.status     := dpath.io.ctrl.status
     vitlb.io.cpu.req_val    := vu.io.imem_req.valid  
@@ -147,11 +150,20 @@ class rocketProc extends Component
     // handle vitlb.io.cpu.exception
     io.vimem.itlb_miss      := vitlb.io.cpu.resp_miss
 
-    vu.io.vec_cmdq <> dpath.io.vcmdq
+    // hooking up vector command queues
-    vu.io.vec_ximm1q <> dpath.io.vximm1q
+    vu.io.vec_cmdq.valid := ctrl.io.vec_iface.vcmdq_valid
-    vu.io.vec_ximm2q <> dpath.io.vximm2q
+    vu.io.vec_cmdq.bits := dpath.io.vec_iface.vcmdq_bits
+    vu.io.vec_ximm1q.valid := ctrl.io.vec_iface.vximm1q_valid
+    vu.io.vec_ximm1q.bits := dpath.io.vec_iface.vximm1q_bits
+    vu.io.vec_ximm2q.valid := ctrl.io.vec_iface.vximm2q_valid
+    vu.io.vec_ximm2q.bits := dpath.io.vec_iface.vximm2q_bits
+
+    ctrl.io.vec_iface.vcmdq_ready := vu.io.vec_cmdq.ready
+    ctrl.io.vec_iface.vximm1q_ready := vu.io.vec_ximm1q.ready
+    ctrl.io.vec_iface.vximm2q_ready := vu.io.vec_ximm2q.ready
     vu.io.vec_ackq.ready := Bool(true)
 
+    // hooking up vector memory interface
     ctrl.io.ext_mem.req_val := vu.io.dmem_req.valid
     ctrl.io.ext_mem.req_cmd := vu.io.dmem_req.bits.cmd
     ctrl.io.ext_mem.req_type := vu.io.dmem_req.bits.typ

rocket/src/main/scala/ctrl.scala

@@ -92,6 +92,8 @@ class ioCtrlAll extends Bundle()
   val xcpt_ma_ld = Bool(INPUT);
   val xcpt_ma_st = Bool(INPUT);
   val fpu = new ioCtrlFPU();
+  val vec_dpath = new ioCtrlDpathVec()
+  val vec_iface = new ioCtrlVecInterface()
 }
 
 class rocketCtrl extends Component
@@ -570,6 +572,17 @@ class rocketCtrl extends Component
                    io.fpu.dec.wen  && fp_sboard.io.r(3).data
   } 
 
+  if (HAVE_VEC)
+  {
+    // vector control
+    val vec = new rocketCtrlVec()
+
+    io.vec_dpath <> vec.io.dpath
+    io.vec_iface <> vec.io.iface
+
+    vec.io.sr_ev := io.dpath.status(SR_EV)
+  }
+
   // exception handling
   // FIXME: verify PC in MEM stage points to valid, restartable instruction
   val p_irq_timer = (io.dpath.status(15).toBool && io.dpath.irq_timer);
@@ -718,6 +731,7 @@ class rocketCtrl extends Component
       id_stall_raddr1 || id_stall_raddr2 || id_stall_waddr ||
       id_stall_fpu || io.ext_mem.req_val ||
       id_mem_val.toBool && !(io.dmem.req_rdy && io.dtlb_rdy) ||
+      id_vec_val.toBool && !(io.vec_iface.vcmdq_ready && io.vec_iface.vximm1q_ready && io.vec_iface.vximm2q_ready) || // being conservative
       ((id_sync === SYNC_D) || (id_sync === SYNC_I)) && !io.dmem.req_rdy ||
       id_console_out_val && !io.console.rdy
     );

rocket/src/main/scala/ctrl_vec.scala

@@ -0,0 +1,103 @@
+package Top
+
+import Chisel._
+import Node._
+import Constants._
+import Instructions._
+
+class ioCtrlDpathVec extends Bundle
+{
+  val valid = Bool(INPUT)
+  val inst = Bits(32, INPUT)
+  val appvl0 = Bool(INPUT)
+  val wen = Bool(OUTPUT)
+  val fn = Bits(1, OUTPUT)
+  val sel_vcmd = Bits(3, OUTPUT)
+  val sel_vimm = Bits(1, OUTPUT)
+}
+
+class ioCtrlVecInterface extends Bundle
+{
+  val vcmdq_valid = Bool(OUTPUT)
+  val vcmdq_ready = Bool(INPUT)
+  val vximm1q_valid = Bool(OUTPUT)
+  val vximm1q_ready = Bool(INPUT)
+  val vximm2q_valid = Bool(OUTPUT)
+  val vximm2q_ready = Bool(INPUT)
+}
+
+class ioCtrlVec extends Bundle
+{
+  val dpath = new ioCtrlDpathVec()
+  val iface = new ioCtrlVecInterface()
+  val sr_ev = Bool(INPUT)
+}
+
+class rocketCtrlVec extends Component
+{
+  val io = new ioCtrlVec()
+
+  val veccs =
+  ListLookup(io.dpath.inst,
+                //                                 appvlmask
+                //                                 | vcmdq
+                //                       wen       | | vximm1q
+                // val vcmd    vimm      | fn      | | | vximm2q
+                //   | |       |         | |       | | | |
+                List(N,VCMD_X, VIMM_X,   N,VEC_X  ,N,N,N,N),Array(
+    VVCFGIVL->  List(Y,VCMD_I, VIMM_VLEN,Y,VEC_CFG,N,Y,Y,N),
+    VSETVL->    List(Y,VCMD_I, VIMM_VLEN,Y,VEC_VL ,N,Y,Y,N),
+    VF->        List(Y,VCMD_I, VIMM_ALU, N,VEC_X  ,Y,Y,Y,N),
+    VMVV->      List(Y,VCMD_TX,VIMM_X,   N,VEC_X  ,Y,Y,N,N),
+    VMSV->      List(Y,VCMD_TX,VIMM_ALU, N,VEC_X  ,Y,Y,Y,N),
+    VFMVV->     List(Y,VCMD_TF,VIMM_X,   N,VEC_X  ,Y,Y,N,N),
+    FENCE_L_V-> List(Y,VCMD_F, VIMM_X,   N,VEC_X  ,N,Y,N,N),
+    FENCE_G_V-> List(Y,VCMD_F, VIMM_X,   N,VEC_X  ,N,Y,N,N),
+    FENCE_L_CV->List(Y,VCMD_F, VIMM_X,   N,VEC_X  ,N,Y,N,N),
+    FENCE_G_CV->List(Y,VCMD_F, VIMM_X,   N,VEC_X  ,N,Y,N,N),
+    VLD->       List(Y,VCMD_MX,VIMM_ALU, N,VEC_X  ,Y,Y,Y,N),
+    VLW->       List(Y,VCMD_MX,VIMM_ALU, N,VEC_X  ,Y,Y,Y,N),
+    VLWU->      List(Y,VCMD_MX,VIMM_ALU, N,VEC_X  ,Y,Y,Y,N),
+    VLH->       List(Y,VCMD_MX,VIMM_ALU, N,VEC_X  ,Y,Y,Y,N),
+    VLHU->      List(Y,VCMD_MX,VIMM_ALU, N,VEC_X  ,Y,Y,Y,N),
+    VLB->       List(Y,VCMD_MX,VIMM_ALU, N,VEC_X  ,Y,Y,Y,N),
+    VLBU->      List(Y,VCMD_MX,VIMM_ALU, N,VEC_X  ,Y,Y,Y,N),
+    VSD->       List(Y,VCMD_MX,VIMM_ALU, N,VEC_X  ,Y,Y,Y,N),
+    VSW->       List(Y,VCMD_MX,VIMM_ALU, N,VEC_X  ,Y,Y,Y,N),
+    VSH->       List(Y,VCMD_MX,VIMM_ALU, N,VEC_X  ,Y,Y,Y,N),
+    VSB->       List(Y,VCMD_MX,VIMM_ALU, N,VEC_X  ,Y,Y,Y,N),
+    VFLD->      List(Y,VCMD_MF,VIMM_ALU, N,VEC_X  ,Y,Y,Y,N),
+    VFLW->      List(Y,VCMD_MF,VIMM_ALU, N,VEC_X  ,Y,Y,Y,N),
+    VFSD->      List(Y,VCMD_MF,VIMM_ALU, N,VEC_X  ,Y,Y,Y,N),
+    VFSW->      List(Y,VCMD_MF,VIMM_ALU, N,VEC_X  ,Y,Y,Y,N),
+    VLSTD->     List(Y,VCMD_MX,VIMM_ALU, N,VEC_X  ,Y,Y,Y,Y),
+    VLSTW->     List(Y,VCMD_MX,VIMM_ALU, N,VEC_X  ,Y,Y,Y,Y),
+    VLSTWU->    List(Y,VCMD_MX,VIMM_ALU, N,VEC_X  ,Y,Y,Y,Y),
+    VLSTH->     List(Y,VCMD_MX,VIMM_ALU, N,VEC_X  ,Y,Y,Y,Y),
+    VLSTHU->    List(Y,VCMD_MX,VIMM_ALU, N,VEC_X  ,Y,Y,Y,Y),
+    VLSTB->     List(Y,VCMD_MX,VIMM_ALU, N,VEC_X  ,Y,Y,Y,Y),
+    VLSTBU->    List(Y,VCMD_MX,VIMM_ALU, N,VEC_X  ,Y,Y,Y,Y),
+    VSSTD->     List(Y,VCMD_MX,VIMM_ALU, N,VEC_X  ,Y,Y,Y,Y),
+    VSSTW->     List(Y,VCMD_MX,VIMM_ALU, N,VEC_X  ,Y,Y,Y,Y),
+    VSSTH->     List(Y,VCMD_MX,VIMM_ALU, N,VEC_X  ,Y,Y,Y,Y),
+    VSSTB->     List(Y,VCMD_MX,VIMM_ALU, N,VEC_X  ,Y,Y,Y,Y),
+    VFLSTD->    List(Y,VCMD_MF,VIMM_ALU, N,VEC_X  ,Y,Y,Y,Y),
+    VFLSTW->    List(Y,VCMD_MF,VIMM_ALU, N,VEC_X  ,Y,Y,Y,Y),
+    VFSSTD->    List(Y,VCMD_MF,VIMM_ALU, N,VEC_X  ,Y,Y,Y,Y),
+    VFSSTW->    List(Y,VCMD_MF,VIMM_ALU, N,VEC_X  ,Y,Y,Y,Y)
+  ))
+
+  val wb_vec_val :: wb_sel_vcmd :: wb_sel_vimm :: wb_vec_wen :: wb_vec_fn :: wb_vec_appvlmask :: veccs0 = veccs
+  val wb_vec_cmdq_val :: wb_vec_ximm1q_val :: wb_vec_ximm2q_val :: Nil = veccs0
+
+  val valid_common = io.dpath.valid && io.sr_ev && wb_vec_val.toBool && !(wb_vec_appvlmask.toBool && io.dpath.appvl0)
+
+  io.iface.vcmdq_valid := valid_common && wb_vec_cmdq_val
+  io.iface.vximm1q_valid := valid_common && wb_vec_ximm1q_val
+  io.iface.vximm2q_valid := valid_common && wb_vec_ximm2q_val
+
+  io.dpath.wen := wb_vec_wen.toBool
+  io.dpath.fn := wb_vec_fn
+  io.dpath.sel_vcmd := wb_sel_vcmd
+  io.dpath.sel_vimm := wb_sel_vimm
+}

rocket/src/main/scala/dpath.scala

@@ -36,12 +36,11 @@ class ioDpathAll extends Bundle()
   val dmem  = new ioDpathDmem();
   val ext_mem = new ioDmem(List("req_val", "req_idx", "req_ppn", "req_data", "req_tag", "resp_val", "resp_data", "resp_tag"))
   val imem  = new ioDpathImem();
-  val vcmdq = new io_vec_cmdq()
-  val vximm1q = new io_vec_ximm1q()
-  val vximm2q = new io_vec_ximm2q()
   val ptbr_wen = Bool(OUTPUT);
   val ptbr = UFix(PADDR_BITS, OUTPUT);
   val fpu = new ioDpathFPU();
+  val vec_ctrl = new ioCtrlDpathVec().flip()
+  val vec_iface = new ioDpathVecInterface()
 }
 
 class rocketDpath extends Component
@@ -55,8 +54,6 @@ class rocketDpath extends Component
   val pcr = new rocketDpathPCR(); 
   val ex_pcr = pcr.io.r.data;
 
-  val vec = new rocketDpathVec()
-
   val alu = new rocketDpathALU(); 
   val ex_alu_out = alu.io.out; 
   val ex_alu_adder_out = alu.io.adder_out; 
@@ -425,9 +422,18 @@ class rocketDpath extends Component
     wb_reg_ctrl_wen_pcr 	:= mem_reg_ctrl_wen_pcr;
   }
 
+  // regfile write
+  val wb_src_dmem = Reg(io.ctrl.mem_load) && wb_reg_valid || r_dmem_resp_replay
+
+  if (HAVE_VEC)
+  {
     // vector datapath
+    val vec = new rocketDpathVec()
+
+    vec.io.ctrl <> io.vec_ctrl
+    io.vec_iface <> vec.io.iface 
+
     vec.io.valid := wb_reg_valid
-  vec.io.sr_ev := pcr.io.status(SR_EV)
     vec.io.inst := wb_reg_inst
     vec.io.waddr := wb_reg_waddr
     vec.io.raddr1 := wb_reg_raddr1
@@ -436,12 +442,17 @@ class rocketDpath extends Component
     vec.io.wdata := wb_reg_wdata
     vec.io.rs2 := wb_reg_rs2
 
-	// regfile write
-  val wb_src_dmem = Reg(io.ctrl.mem_load) && wb_reg_valid || r_dmem_resp_replay
     wb_wdata :=
       Mux(vec.io.wen, Cat(Bits(0,52), vec.io.appvl),
       Mux(wb_src_dmem, io.dmem.resp_data_subword,
       wb_reg_wdata))
+  }
+  else
+  {
+    wb_wdata :=
+      Mux(wb_src_dmem, io.dmem.resp_data_subword,
+      wb_reg_wdata)
+  }
 
   rfile.io.w0.addr := wb_reg_waddr
   rfile.io.w0.en   := io.ctrl.wb_wen || wb_reg_ll_wb
@@ -454,10 +465,6 @@ class rocketDpath extends Component
   io.ctrl.wb_waddr := wb_reg_waddr;
   io.ctrl.mem_wb := dmem_resp_replay;
 
-  vec.io.vcmdq <> io.vcmdq
-  vec.io.vximm1q <> io.vximm1q
-  vec.io.vximm2q <> io.vximm2q
-  
   // scoreboard clear (for div/mul and D$ load miss writebacks)
   io.ctrl.sboard_clr   := mem_ll_wb
   io.ctrl.sboard_clra  := mem_ll_waddr

rocket/src/main/scala/dpath_vec.scala

@@ -4,12 +4,20 @@ import Chisel._
 import Node._
 import Constants._
 import Instructions._
-import hwacha._
+import hwacha.Interface._
+
+class ioDpathVecInterface extends Bundle
+{
+  val vcmdq_bits = Bits(VCMD_SZ, OUTPUT)
+  val vximm1q_bits = Bits(VIMM_SZ, OUTPUT)
+  val vximm2q_bits = Bits(VSTRIDE_SZ, OUTPUT)
+}
 
 class ioDpathVec extends Bundle
 {
+  val ctrl = new ioCtrlDpathVec().flip()
+  val iface = new ioDpathVecInterface()
   val valid = Bool(INPUT)
-  val sr_ev = Bool(INPUT)
   val inst = Bits(32, INPUT)
   val waddr = UFix(5, INPUT)
   val raddr1 = UFix(5, INPUT)
@@ -19,68 +27,12 @@ class ioDpathVec extends Bundle
   val rs2 = Bits(64, INPUT)
   val wen = Bool(OUTPUT)
   val appvl = UFix(12, OUTPUT)
-  val vcmdq = new io_vec_cmdq()
-  val vximm1q = new io_vec_ximm1q()
-  val vximm2q = new io_vec_ximm2q()
 }
 
 class rocketDpathVec extends Component
 {
   val io = new ioDpathVec()
 
-  val veccs =
-  ListLookup(io.inst,
-                //                                 appvlmask
-                //                                 | vcmdq
-                //                       wen       | | vximm1q
-                // val vcmd    vimm      | fn      | | | vximm2q
-                //   | |       |         | |       | | | |
-                List(N,VCMD_X, VIMM_X,   N,VEC_X  ,N,N,N,N),Array(
-    VVCFGIVL->  List(Y,VCMD_I, VIMM_VLEN,Y,VEC_CFG,N,Y,Y,N),
-    VSETVL->    List(Y,VCMD_I, VIMM_VLEN,Y,VEC_VL ,N,Y,Y,N),
-    VF->        List(Y,VCMD_I, VIMM_ALU, N,VEC_X  ,Y,Y,Y,N),
-    VMVV->      List(Y,VCMD_TX,VIMM_X,   N,VEC_X  ,Y,Y,N,N),
-    VMSV->      List(Y,VCMD_TX,VIMM_ALU, N,VEC_X  ,Y,Y,Y,N),
-    VFMVV->     List(Y,VCMD_TF,VIMM_X,   N,VEC_X  ,Y,Y,N,N),
-    FENCE_L_V-> List(Y,VCMD_F, VIMM_X,   N,VEC_X  ,N,Y,N,N),
-    FENCE_G_V-> List(Y,VCMD_F, VIMM_X,   N,VEC_X  ,N,Y,N,N),
-    FENCE_L_CV->List(Y,VCMD_F, VIMM_X,   N,VEC_X  ,N,Y,N,N),
-    FENCE_G_CV->List(Y,VCMD_F, VIMM_X,   N,VEC_X  ,N,Y,N,N),
-    VLD->       List(Y,VCMD_MX,VIMM_ALU, N,VEC_X  ,Y,Y,Y,N),
-    VLW->       List(Y,VCMD_MX,VIMM_ALU, N,VEC_X  ,Y,Y,Y,N),
-    VLWU->      List(Y,VCMD_MX,VIMM_ALU, N,VEC_X  ,Y,Y,Y,N),
-    VLH->       List(Y,VCMD_MX,VIMM_ALU, N,VEC_X  ,Y,Y,Y,N),
-    VLHU->      List(Y,VCMD_MX,VIMM_ALU, N,VEC_X  ,Y,Y,Y,N),
-    VLB->       List(Y,VCMD_MX,VIMM_ALU, N,VEC_X  ,Y,Y,Y,N),
-    VLBU->      List(Y,VCMD_MX,VIMM_ALU, N,VEC_X  ,Y,Y,Y,N),
-    VSD->       List(Y,VCMD_MX,VIMM_ALU, N,VEC_X  ,Y,Y,Y,N),
-    VSW->       List(Y,VCMD_MX,VIMM_ALU, N,VEC_X  ,Y,Y,Y,N),
-    VSH->       List(Y,VCMD_MX,VIMM_ALU, N,VEC_X  ,Y,Y,Y,N),
-    VSB->       List(Y,VCMD_MX,VIMM_ALU, N,VEC_X  ,Y,Y,Y,N),
-    VFLD->      List(Y,VCMD_MF,VIMM_ALU, N,VEC_X  ,Y,Y,Y,N),
-    VFLW->      List(Y,VCMD_MF,VIMM_ALU, N,VEC_X  ,Y,Y,Y,N),
-    VFSD->      List(Y,VCMD_MF,VIMM_ALU, N,VEC_X  ,Y,Y,Y,N),
-    VFSW->      List(Y,VCMD_MF,VIMM_ALU, N,VEC_X  ,Y,Y,Y,N),
-    VLSTD->     List(Y,VCMD_MX,VIMM_ALU, N,VEC_X  ,Y,Y,Y,Y),
-    VLSTW->     List(Y,VCMD_MX,VIMM_ALU, N,VEC_X  ,Y,Y,Y,Y),
-    VLSTWU->    List(Y,VCMD_MX,VIMM_ALU, N,VEC_X  ,Y,Y,Y,Y),
-    VLSTH->     List(Y,VCMD_MX,VIMM_ALU, N,VEC_X  ,Y,Y,Y,Y),
-    VLSTHU->    List(Y,VCMD_MX,VIMM_ALU, N,VEC_X  ,Y,Y,Y,Y),
-    VLSTB->     List(Y,VCMD_MX,VIMM_ALU, N,VEC_X  ,Y,Y,Y,Y),
-    VLSTBU->    List(Y,VCMD_MX,VIMM_ALU, N,VEC_X  ,Y,Y,Y,Y),
-    VSSTD->     List(Y,VCMD_MX,VIMM_ALU, N,VEC_X  ,Y,Y,Y,Y),
-    VSSTW->     List(Y,VCMD_MX,VIMM_ALU, N,VEC_X  ,Y,Y,Y,Y),
-    VSSTH->     List(Y,VCMD_MX,VIMM_ALU, N,VEC_X  ,Y,Y,Y,Y),
-    VSSTB->     List(Y,VCMD_MX,VIMM_ALU, N,VEC_X  ,Y,Y,Y,Y),
-    VFLSTD->    List(Y,VCMD_MF,VIMM_ALU, N,VEC_X  ,Y,Y,Y,Y),
-    VFLSTW->    List(Y,VCMD_MF,VIMM_ALU, N,VEC_X  ,Y,Y,Y,Y),
-    VFSSTD->    List(Y,VCMD_MF,VIMM_ALU, N,VEC_X  ,Y,Y,Y,Y),
-    VFSSTW->    List(Y,VCMD_MF,VIMM_ALU, N,VEC_X  ,Y,Y,Y,Y)
-  ))
-
-  val wb_vec_val :: wb_sel_vcmd :: wb_sel_vimm :: wb_vec_wen :: wb_vec_fn :: wb_vec_appvlmask :: veccs0 = veccs
-  val wb_vec_cmdq_val :: wb_vec_ximm1q_val :: wb_vec_ximm2q_val :: Nil = veccs0
-
   val nxregs = Cat(UFix(0,1),io.inst(15,10).toUFix) // FIXME: to make the nregs width 7 bits
   val nfregs = io.inst(21,16).toUFix
   val nregs = nxregs + nfregs
@@ -145,37 +97,35 @@ class rocketDpathVec extends Component
   val reg_hwvl = Reg(resetVal = UFix(32, 12))
   val reg_appvl0 = Reg(resetVal = Bool(true))
   val hwvl_vcfg = (uts_per_bank * io.vecbankcnt)(11,0)
-  val hwvl = Mux(wb_vec_fn.toBool, hwvl_vcfg, reg_hwvl)
+  val hwvl = Mux(io.ctrl.fn === VEC_CFG, hwvl_vcfg, reg_hwvl)
   val appvl = Mux(io.wdata(11,0) < hwvl, io.wdata(11,0), hwvl).toUFix
 
-  when (io.valid && wb_vec_wen.toBool && wb_vec_fn.toBool)
+  when (io.valid && io.ctrl.wen && (io.ctrl.fn === VEC_CFG))
   {
     reg_hwvl := hwvl_vcfg
     reg_appvl0 := !(appvl.orR())
   }
 
-  io.wen := io.valid && wb_vec_wen.toBool
+  io.wen := io.valid && io.ctrl.wen
   io.appvl := appvl
   val vlenm1 = appvl - Bits(1,1)
 
-  val valid_common = io.valid && io.sr_ev && wb_vec_val.toBool && !(wb_vec_appvlmask.toBool && reg_appvl0)
+  io.iface.vcmdq_bits :=
-
+    Mux(io.ctrl.sel_vcmd === VCMD_I, Cat(Bits(0,2), Bits(0,4), io.inst(9,8), Bits(0,6), Bits(0,6)),
-  io.vcmdq.valid := valid_common && wb_vec_cmdq_val
+    Mux(io.ctrl.sel_vcmd === VCMD_F, Cat(Bits(0,2), Bits(1,3), io.inst(9,7), Bits(0,6), Bits(0,6)),
-  io.vximm1q.valid := valid_common && wb_vec_ximm1q_val
+    Mux(io.ctrl.sel_vcmd === VCMD_TX, Cat(Bits(1,2), io.inst(13,8), Bits(0,1), io.waddr, Bits(0,1), io.raddr1),
-  io.vximm2q.valid := valid_common && wb_vec_ximm2q_val
+    Mux(io.ctrl.sel_vcmd === VCMD_TF, Cat(Bits(1,2), io.inst(13,8), Bits(1,1), io.waddr, Bits(1,1), io.raddr1),
-
+    Mux(io.ctrl.sel_vcmd === VCMD_MX, Cat(Bits(1,1), io.inst(13,12), io.inst(2), io.inst(10,7), Bits(0,1), io.waddr, Bits(0,1), io.waddr),
-  io.vcmdq.bits :=
+    Mux(io.ctrl.sel_vcmd === VCMD_MF, Cat(Bits(1,1), io.inst(13,12), io.inst(2), io.inst(10,7), Bits(1,1), io.waddr, Bits(1,1), io.waddr),
-    Mux(wb_sel_vcmd === VCMD_I, Cat(Bits(0,2), Bits(0,4), io.inst(9,8), Bits(0,6), Bits(0,6)),
-    Mux(wb_sel_vcmd === VCMD_F, Cat(Bits(0,2), Bits(1,3), io.inst(9,7), Bits(0,6), Bits(0,6)),
-    Mux(wb_sel_vcmd === VCMD_TX, Cat(Bits(1,2), io.inst(13,8), Bits(0,1), io.waddr, Bits(0,1), io.raddr1),
-    Mux(wb_sel_vcmd === VCMD_TF, Cat(Bits(1,2), io.inst(13,8), Bits(1,1), io.waddr, Bits(1,1), io.raddr1),
-    Mux(wb_sel_vcmd === VCMD_MX, Cat(Bits(1,1), io.inst(13,12), io.inst(2), io.inst(10,7), Bits(0,1), io.waddr, Bits(0,1), io.waddr),
-    Mux(wb_sel_vcmd === VCMD_MF, Cat(Bits(1,1), io.inst(13,12), io.inst(2), io.inst(10,7), Bits(1,1), io.waddr, Bits(1,1), io.waddr),
     Bits(0,20)))))))
 
-  io.vximm1q.bits :=
+  io.iface.vximm1q_bits :=
-    Mux(wb_sel_vimm === VIMM_VLEN, Cat(Bits(0,29), io.vecbankcnt, io.vecbank, io.inst(21,10), vlenm1(10,0)),
+    Mux(io.ctrl.sel_vimm === VIMM_VLEN, Cat(Bits(0,29), io.vecbankcnt, io.vecbank, io.inst(21,10), vlenm1(10,0)),
     io.wdata) // VIMM_ALU
 
-  io.vximm2q.bits := io.rs2
+  io.iface.vximm2q_bits := io.rs2
+
+  io.ctrl.valid := io.valid
+  io.ctrl.inst := io.inst
+  io.ctrl.appvl0 := reg_appvl0
 }