tilelink: unsafe cache cork discards outer d.sink
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@ -98,6 +98,7 @@ class TLCacheCork(unsafe: Boolean = false)(implicit p: Parameters) extends LazyM
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val d_d = Wire(in.d)
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val d_d = Wire(in.d)
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d_d <> out.d
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d_d <> out.d
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d_d.bits.source := out.d.bits.source >> 1
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d_d.bits.source := out.d.bits.source >> 1
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if (unsafe) { d_d.bits.sink := UInt(0) }
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when (out.d.bits.opcode === AccessAckData && out.d.bits.source(0)) {
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when (out.d.bits.opcode === AccessAckData && out.d.bits.source(0)) {
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d_d.bits.opcode := GrantData
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d_d.bits.opcode := GrantData
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