riscv/rocket-chip
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tile: BaseTileModule => BaseTileModuleImp

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This commit is contained in:
Henry Cook
2018-01-02 17:55:54 -08:00
parent b0e1bc3071
commit 320900f76c
5 changed files with 9 additions and 9 deletions
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4
src/main/scala/tile/BaseTile.scala
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@ -125,7 +125,7 @@ trait HasTileParameters {
abstract class BaseTile(tileParams: TileParams, val crossing: CoreplexClockCrossing)
(implicit p: Parameters) extends LazyModule with HasTileParameters with HasCrossing
{
def module: BaseTileModule[BaseTile]
def module: BaseTileModuleImp[BaseTile]
def masterNode: TLOutwardNode
def slaveNode: TLInwardNode
def intInwardNode: IntInwardNode
@ -171,7 +171,7 @@ abstract class BaseTile(tileParams: TileParams, val crossing: CoreplexClockCross
}
}
class BaseTileModule[+L <: BaseTile](val outer: L) extends LazyModuleImp(outer) with HasTileParameters {
class BaseTileModuleImp[+L <: BaseTile](val outer: L) extends LazyModuleImp(outer) with HasTileParameters {
require(xLen == 32 || xLen == 64)
require(paddrBits <= maxPAddrBits)