riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

tile: BaseTileModule => BaseTileModuleImp

Browse Source
This commit is contained in:
Henry Cook
2018-01-02 17:55:54 -08:00
parent b0e1bc3071
commit 320900f76c
5 changed files with 9 additions and 9 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
src/main/scala/tile/BaseTile.scala
View File

@@ -125,7 +125,7 @@ trait HasTileParameters {
abstract class BaseTile(tileParams: TileParams, val crossing: CoreplexClockCrossing)
(implicit p: Parameters) extends LazyModule with HasTileParameters with HasCrossing
{
def module: BaseTileModule[BaseTile]
def module: BaseTileModuleImp[BaseTile]
def masterNode: TLOutwardNode
def slaveNode: TLInwardNode
def intInwardNode: IntInwardNode
@@ -171,7 +171,7 @@ abstract class BaseTile(tileParams: TileParams, val crossing: CoreplexClockCross
}
}
class BaseTileModule[+L <: BaseTile](val outer: L) extends LazyModuleImp(outer) with HasTileParameters {
class BaseTileModuleImp[+L <: BaseTile](val outer: L) extends LazyModuleImp(outer) with HasTileParameters {
require(xLen == 32 || xLen == 64)
require(paddrBits <= maxPAddrBits)

2
src/main/scala/tile/LazyRoCC.scala
View File

@@ -91,7 +91,7 @@ trait HasLazyRoCC extends CanHavePTW { this: BaseTile =>
}
trait HasLazyRoCCModule[+L <: BaseTile with HasLazyRoCC] extends CanHavePTWModule
with HasCoreParameters { this: BaseTileModule[L] =>
with HasCoreParameters { this: BaseTileModuleImp[L] =>
val roccCore = Wire(new RoCCCoreIO()(outer.p))

4
src/main/scala/tile/RocketTile.scala
View File

@@ -92,10 +92,10 @@ class RocketTile(
Resource(cpuDevice, "reg").bind(ResourceInt(BigInt(hartId)))
}
override lazy val module = new RocketTileModule(this)
override lazy val module = new RocketTileModuleImp(this)
}
class RocketTileModule(outer: RocketTile) extends BaseTileModule(outer)
class RocketTileModuleImp(outer: RocketTile) extends BaseTileModuleImp(outer)
with HasLazyRoCCModule[RocketTile]
with HasHellaCacheModule
with HasICacheFrontendModule {