riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

tile: BaseTileModule => BaseTileModuleImp

Browse Source
This commit is contained in:
Henry Cook
2018-01-02 17:55:54 -08:00
parent b0e1bc3071
commit 320900f76c
5 changed files with 9 additions and 9 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
src/main/scala/groundtest/TraceGen.scala
View File

@ -580,10 +580,10 @@ class TraceGenerator(val params: TraceGenParams)(implicit val p: Parameters) ext
class TraceGenTile(val id: Int, val params: TraceGenParams)(implicit p: Parameters) extends GroundTestTile(params) {
val masterNode: TLOutwardNode = dcacheOpt.map(_.node).getOrElse(TLIdentityNode())
override lazy val module = new TraceGenTileModule(this)
override lazy val module = new TraceGenTileModuleImp(this)
}
class TraceGenTileModule(outer: TraceGenTile) extends GroundTestTileModule(outer) {
class TraceGenTileModuleImp(outer: TraceGenTile) extends GroundTestTileModuleImp(outer) {
val tracegen = Module(new TraceGenerator(outer.params))
tracegen.io.hartid := constants.hartid