riscv/rocket-chip
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tile: BaseTileModule => BaseTileModuleImp

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This commit is contained in:
Henry Cook
2018-01-02 17:55:54 -08:00
parent b0e1bc3071
commit 320900f76c
5 changed files with 9 additions and 9 deletions
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4
src/main/scala/groundtest/Tile.scala
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@ -39,10 +39,10 @@ abstract class GroundTestTile(params: GroundTestTileParams)
val dcacheOpt = params.dcache.map { dc => LazyModule(new DCache(0)) }
override lazy val module = new GroundTestTileModule(this)
override lazy val module = new GroundTestTileModuleImp(this)
}
class GroundTestTileModule(outer: GroundTestTile) extends BaseTileModule(outer) {
class GroundTestTileModuleImp(outer: GroundTestTile) extends BaseTileModuleImp(outer) {
val status = IO(new GroundTestStatus)
val halt_and_catch_fire = None

4
src/main/scala/groundtest/TraceGen.scala
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@ -580,10 +580,10 @@ class TraceGenerator(val params: TraceGenParams)(implicit val p: Parameters) ext
class TraceGenTile(val id: Int, val params: TraceGenParams)(implicit p: Parameters) extends GroundTestTile(params) {
val masterNode: TLOutwardNode = dcacheOpt.map(_.node).getOrElse(TLIdentityNode())
override lazy val module = new TraceGenTileModule(this)
override lazy val module = new TraceGenTileModuleImp(this)
}
class TraceGenTileModule(outer: TraceGenTile) extends GroundTestTileModule(outer) {
class TraceGenTileModuleImp(outer: TraceGenTile) extends GroundTestTileModuleImp(outer) {
val tracegen = Module(new TraceGenerator(outer.params))
tracegen.io.hartid := constants.hartid