From 31f0b600fd5c72312f9d8e8d31d132f625976b8b Mon Sep 17 00:00:00 2001
From: Andrew Waterman <waterman@eecs.berkeley.edu>
Date: Sun, 25 Mar 2012 23:03:20 -0700
Subject: [PATCH] add dessert

---
 rocket/src/main/scala/memserdes.scala | 117 ++++++++++++++++++++------
 rocket/src/main/scala/top.scala       |   5 +-
 2 files changed, 95 insertions(+), 27 deletions(-)

diff --git a/rocket/src/main/scala/memserdes.scala b/rocket/src/main/scala/memserdes.scala
index 2305ed69..f68d36e8 100644
--- a/rocket/src/main/scala/memserdes.scala
+++ b/rocket/src/main/scala/memserdes.scala
@@ -27,14 +27,28 @@ class MemSerdes(w: Int) extends Component
   val s_idle :: s_read_addr :: s_write_addr :: s_write_idle :: s_write_data :: Nil = Enum(5) { UFix() }
   val state = Reg(resetVal = s_idle)
   val send_cnt = Reg(resetVal = UFix(0, log2up(max(abits, dbits))))
-  val data_send_cnt = Reg(resetVal = UFix(0, log2up(MEM_DATA_BITS)))
+  val data_send_cnt = Reg(resetVal = UFix(0, log2up(REFILL_CYCLES)))
   val adone = io.narrow.req.ready && send_cnt === UFix((abits-1)/w)
   val ddone = io.narrow.req.ready && send_cnt === UFix((dbits-1)/w)
 
-  when (state === s_idle) {
-    when (io.wide.req_cmd.valid) {
-      state := Mux(io.wide.req_cmd.bits.rw, s_write_addr, s_read_addr)
-    }
+  when (io.narrow.req.valid && io.narrow.req.ready) {
+    send_cnt := send_cnt + UFix(1)
+    out_buf := out_buf >> UFix(w)
+  }
+  when (io.wide.req_cmd.valid && io.wide.req_cmd.ready) {
+    out_buf := io.wide.req_cmd.bits.toBits
+  }
+  when (io.wide.req_data.valid && io.wide.req_data.ready) {
+    out_buf := io.wide.req_data.bits.toBits
+  }
+
+  io.wide.req_cmd.ready := state === s_idle
+  io.wide.req_data.ready := state === s_write_idle
+  io.narrow.req.valid := state === s_read_addr || state === s_write_addr || state === s_write_data
+  io.narrow.req.bits := out_buf
+
+  when (state === s_idle && io.wide.req_cmd.valid) {
+    state := Mux(io.wide.req_cmd.bits.rw, s_write_addr, s_read_addr)
   }
   when (state === s_read_addr && adone) {
     state := s_idle
@@ -50,26 +64,11 @@ class MemSerdes(w: Int) extends Component
   when (state === s_write_data && ddone) {
     data_send_cnt := data_send_cnt + UFix(1)
     state := Mux(data_send_cnt === UFix(REFILL_CYCLES-1), s_idle, s_write_idle)
+    send_cnt := UFix(0)
   }
 
-  when (io.narrow.req.valid && io.narrow.req.ready) {
-    send_cnt := Mux(adone, UFix(0), send_cnt + UFix(1))
-    out_buf := out_buf >> UFix(w)
-  }
-  when (io.wide.req_cmd.valid && io.wide.req_cmd.ready) {
-    out_buf := io.wide.req_cmd.bits.toBits
-  }
-  when (io.wide.req_data.valid && io.wide.req_data.ready) {
-    out_buf := io.wide.req_data.bits.toBits
-  }
-
-  io.wide.req_cmd.ready := state === s_idle
-  io.wide.req_data.ready := state === s_write_idle
-  io.narrow.req.valid := state === s_read_addr || state === s_write_addr || state === s_write_data
-  io.narrow.req.bits := out_buf
-
-  val recv_cnt = Reg() { UFix(width = log2up(rbits)) }
-  val data_recv_cnt = Reg(resetVal = UFix(0, log2up(MEM_DATA_BITS)))
+  val recv_cnt = Reg(resetVal = UFix(0, log2up((rbits+w-1)/w)))
+  val data_recv_cnt = Reg(resetVal = UFix(0, log2up(REFILL_CYCLES)))
   val resp_val = Reg(resetVal = Bool(false))
 
   resp_val := Bool(false)
@@ -80,10 +79,80 @@ class MemSerdes(w: Int) extends Component
       data_recv_cnt := data_recv_cnt + UFix(1)
       resp_val := Bool(true)
     }
-    in_buf := Cat(io.narrow.resp.bits, in_buf(rbits-1,w))
+    in_buf := Cat(io.narrow.resp.bits, in_buf((rbits+w-1)/w*w-1,w))
   }
 
   io.wide.resp.valid := resp_val
   io.wide.resp.bits.tag := in_buf(io.wide.resp.bits.tag.width-1,0)
   io.wide.resp.bits.data := in_buf >> UFix(io.wide.resp.bits.tag.width)
 }
+
+class MemDessert(w: Int) extends Component // test rig side
+{
+  val io = new Bundle {
+    val narrow = new ioMemSerialized(w).flip
+    val wide = new ioMem
+  }
+  val abits = io.wide.req_cmd.bits.toBits.getWidth
+  val dbits = io.wide.req_data.bits.toBits.getWidth
+  val rbits = io.wide.resp.bits.getWidth
+
+  require(dbits >= abits && rbits >= dbits)
+  val recv_cnt = Reg(resetVal = UFix(0, log2up(rbits)))
+  val data_recv_cnt = Reg(resetVal = UFix(0, log2up(REFILL_CYCLES)))
+  val adone = io.narrow.req.valid && recv_cnt === UFix((abits-1)/w)
+  val ddone = io.narrow.req.valid && recv_cnt === UFix((dbits-1)/w)
+  val rdone = io.narrow.resp.valid && recv_cnt === UFix((rbits-1)/w)
+
+  val s_cmd_recv :: s_cmd :: s_data_recv :: s_data :: s_reply :: Nil = Enum(5) { UFix() }
+  val state = Reg(resetVal = s_cmd_recv)
+
+  val in_buf = Reg() { Bits() }
+  when (io.narrow.req.valid && io.narrow.req.ready || io.narrow.resp.valid) {
+    recv_cnt := recv_cnt + UFix(1)
+    in_buf := Cat(io.narrow.req.bits, in_buf((rbits+w-1)/w*w-1,w))
+  }
+  io.narrow.req.ready := state === s_cmd_recv || state === s_data_recv
+
+  when (state === s_cmd_recv && adone) {
+    state := s_cmd
+    recv_cnt := UFix(0)
+  }
+  when (state === s_cmd && io.wide.req_cmd.ready) {
+    state := Mux(io.wide.req_cmd.bits.rw, s_data_recv, s_reply)
+  }
+  when (state === s_data_recv && ddone) {
+    state := s_data
+    recv_cnt := UFix(0)
+  }
+  when (state === s_data && io.wide.req_data.ready) {
+    state := s_data_recv
+    when (data_recv_cnt === UFix(REFILL_CYCLES-1)) {
+      state := s_cmd_recv
+    }
+    data_recv_cnt := data_recv_cnt + UFix(1)
+  }
+  when (rdone) { // state === s_reply
+    when (data_recv_cnt === UFix(REFILL_CYCLES-1)) {
+      state := s_cmd_recv
+    }
+    recv_cnt := UFix(0)
+    data_recv_cnt := data_recv_cnt + UFix(1)
+  }
+
+  val req_cmd = in_buf >> UFix(((rbits+w-1)/w - (abits+w-1)/w)*w)
+  io.wide.req_cmd.valid := state === s_cmd
+  io.wide.req_cmd.bits.tag := req_cmd
+  io.wide.req_cmd.bits.addr := req_cmd.toUFix >> UFix(io.wide.req_cmd.bits.tag.width)
+  io.wide.req_cmd.bits.rw := req_cmd(io.wide.req_cmd.bits.tag.width + io.wide.req_cmd.bits.addr.width)
+
+  io.wide.req_data.valid := state === s_data
+  io.wide.req_data.bits.data := in_buf >> UFix(((rbits+w-1)/w - (dbits+w-1)/w)*w)
+
+  val dataq = (new queue(REFILL_CYCLES)) { new MemResp }
+  dataq.io.enq <> io.wide.resp
+  dataq.io.deq.ready := recv_cnt === UFix((rbits-1)/w)
+
+  io.narrow.resp.valid := dataq.io.deq.valid
+  io.narrow.resp.bits := dataq.io.deq.bits.toBits >> (recv_cnt * UFix(w))
+}
diff --git a/rocket/src/main/scala/top.scala b/rocket/src/main/scala/top.scala
index 3f0aa583..ca07147d 100644
--- a/rocket/src/main/scala/top.scala
+++ b/rocket/src/main/scala/top.scala
@@ -45,9 +45,8 @@ class Top() extends Component
   mem_serdes.io.wide.req_data.valid := mem_dataq.io.deq.valid && io.mem_backup_en
   mem_serdes.io.wide.req_data.bits := mem_dataq.io.deq.bits
 
-  // only the main or backup port may respond at any one time
-  hub.io.mem.resp.valid := io.mem.resp.valid || mem_serdes.io.wide.resp.valid
-  hub.io.mem.resp.bits := Mux(io.mem.resp.valid, io.mem.resp.bits, mem_serdes.io.wide.resp.bits)
+  hub.io.mem.resp.valid := Mux(io.mem_backup_en, mem_serdes.io.wide.resp.valid, io.mem.resp.valid)
+  hub.io.mem.resp.bits := Mux(io.mem_backup_en, mem_serdes.io.wide.resp.bits, io.mem.resp.bits)
 
   // pad out the HTIF using a divided clock
   val hio = (new slowIO(clkdiv, 4)) { Bits(width = htif_width) }