riscv/rocket-chip
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add missing "otherwise"

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This commit is contained in:
Andrew Waterman 2012-01-21 20:13:15 -08:00
parent 97f0852b17
commit 31c56228e2
2 changed files with 13 additions and 10 deletions
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2
rocket/src/main/scala/nbdcache.scala
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@ -227,7 +227,9 @@ class MSHR(id: Int) extends Component {
when (io.meta_req.valid && io.meta_req.ready) { when (io.meta_req.valid && io.meta_req.ready) {
valid <== Bool(false) valid <== Bool(false)
} }
otherwise {
dirty <== next_dirty dirty <== next_dirty
}
io.idx_match := valid && (idx_ === io.req_idx) io.idx_match := valid && (idx_ === io.req_idx)
io.idx := idx_ io.idx := idx_

13
rocket/src/main/scala/queues.scala
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@ -28,12 +28,6 @@ class queueCtrl(entries: Int) extends Component
val deq_ptr = Reg(width = addr_sz, resetVal = UFix(0, addr_sz)); val deq_ptr = Reg(width = addr_sz, resetVal = UFix(0, addr_sz));
val full = Reg(width = 1, resetVal = Bool(false)); val full = Reg(width = 1, resetVal = Bool(false));
when (io.q_reset) {
enq_ptr <== UFix(0, addr_sz);
deq_ptr <== UFix(0, addr_sz);
full <== Bool(false);
}
io.waddr := enq_ptr; io.waddr := enq_ptr;
io.raddr := deq_ptr; io.raddr := deq_ptr;
@ -76,10 +70,17 @@ class queueCtrl(entries: Int) extends Component
Mux(do_deq && full, Bool(false), Mux(do_deq && full, Bool(false),
full)); full));
when (io.q_reset) {
enq_ptr <== UFix(0, addr_sz);
deq_ptr <== UFix(0, addr_sz);
full <== Bool(false);
}
otherwise {
enq_ptr <== enq_ptr_next; enq_ptr <== enq_ptr_next;
deq_ptr <== deq_ptr_next; deq_ptr <== deq_ptr_next;
full <== full_next; full <== full_next;
} }
}
class ioQueueSimplePF[T <: Data]()(data: => T) extends Bundle class ioQueueSimplePF[T <: Data]()(data: => T) extends Bundle
{ {