From 3103fa8da20134644ab07b77ad4f8cc5c13754e2 Mon Sep 17 00:00:00 2001
From: Howard Mao <zhehao.mao@gmail.com>
Date: Tue, 27 Oct 2015 16:42:31 -0700
Subject: [PATCH] rename tl to mem in generator

---
 groundtest/src/main/scala/generator.scala | 23 ++++++++-------
 groundtest/src/main/scala/tile.scala      | 36 ++++++++++++++++++-----
 2 files changed, 41 insertions(+), 18 deletions(-)

diff --git a/groundtest/src/main/scala/generator.scala b/groundtest/src/main/scala/generator.scala
index 6307c0d9..0292e1ed 100644
--- a/groundtest/src/main/scala/generator.scala
+++ b/groundtest/src/main/scala/generator.scala
@@ -24,15 +24,15 @@ class UncachedTileLinkGenerator(id: Int)
   private val totalRequests = maxAddress / nGens
 
   val io = new Bundle {
-    val tl = new ClientUncachedTileLinkIO
+    val mem = new ClientUncachedTileLinkIO
     val finished = Bool(OUTPUT)
   }
 
   val (s_start :: s_put :: s_get :: s_finished :: Nil) = Enum(Bits(), 4)
   val state = Reg(init = s_start)
 
-  val (acq_beat, acq_done) = Counter(io.tl.acquire.fire() && state === s_put, tlDataBeats)
-  val (gnt_beat, gnt_done) = Counter(io.tl.grant.fire() && state === s_get, tlDataBeats)
+  val (acq_beat, acq_done) = Counter(io.mem.acquire.fire() && state === s_put, tlDataBeats)
+  val (gnt_beat, gnt_done) = Counter(io.mem.grant.fire() && state === s_get, tlDataBeats)
   val (req_cnt, req_wrap) = Counter(gnt_done && state === s_get, totalRequests)
 
   val addr_block = Cat(req_cnt, UInt(id, log2Up(nGens)))
@@ -46,11 +46,11 @@ class UncachedTileLinkGenerator(id: Int)
 
   when (state === s_put) {
     when (acq_done) { sending := Bool(false) }
-    when (io.tl.grant.fire()) { sending := Bool(true); state := s_get }
+    when (io.mem.grant.fire()) { sending := Bool(true); state := s_get }
   }
 
   when (state === s_get) {
-    when (io.tl.acquire.fire()) { sending := Bool(false) }
+    when (io.mem.acquire.fire()) { sending := Bool(false) }
     when (gnt_done) {
       sending := Bool(true)
       state := Mux(req_wrap, s_finished, s_put)
@@ -75,11 +75,12 @@ class UncachedTileLinkGenerator(id: Int)
     client_xact_id = UInt(0),
     addr_block = addr_block)
 
-  io.tl.acquire.valid := sending
-  io.tl.acquire.bits := Mux(state === s_put, put_acquire, get_acquire)
-  io.tl.grant.ready := !sending
+  io.mem.acquire.valid := sending
+  io.mem.acquire.bits := Mux(state === s_put, put_acquire, get_acquire)
+  io.mem.grant.ready := !sending
 
-  assert(!io.tl.grant.valid || state != s_get ||
-    io.tl.grant.bits.data === get_data,
-    "Get received incorrect data")
+  assert(!io.mem.grant.valid || state != s_get ||
+    io.mem.grant.bits.data === get_data,
+    s"Get received incorrect data in generator ${id}")
 }
+
diff --git a/groundtest/src/main/scala/tile.scala b/groundtest/src/main/scala/tile.scala
index 2f0946e0..c481f68f 100644
--- a/groundtest/src/main/scala/tile.scala
+++ b/groundtest/src/main/scala/tile.scala
@@ -6,6 +6,33 @@ import uncore._
 import scala.util.Random
 import cde.Parameters
 
+/** A "cache" that responds to probe requests with a release indicating
+ *  the block is not present */
+class DummyCache(implicit val p: Parameters) extends Module
+    with HasGeneratorParams {
+  val io = new ClientTileLinkIO
+
+  val req = Reg(new Probe)
+  val coh = ClientMetadata.onReset
+  val (s_probe :: s_release :: Nil) = Enum(Bits(), 2)
+  val state = Reg(init = s_probe)
+
+  io.acquire.valid := Bool(false)
+  io.probe.ready := (state === s_probe)
+  io.grant.ready := Bool(true)
+  io.release.valid := (state === s_release)
+  io.release.bits := coh.makeRelease(req)
+
+  when (io.probe.fire()) {
+    req := io.probe.bits
+    state := s_release
+  }
+
+  when (io.release.fire()) {
+    state := s_probe
+  }
+}
+
 class GeneratorTile(id: Int, resetSignal: Bool)
                    (implicit val p: Parameters) extends Tile(resetSignal)(p)
                    with HasGeneratorParams {
@@ -16,17 +43,12 @@ class GeneratorTile(id: Int, resetSignal: Bool)
   for (i <- 0 until nGensPerTile) {
     val genid = id * nGensPerTile + i
     val generator = Module(new UncachedTileLinkGenerator(genid))
-    arb.io.in(i) <> generator.io.tl
+    arb.io.in(i) <> generator.io.mem
     gen_finished(i) := generator.io.finished
   }
 
   io.uncached(0) <> arb.io.out
-  io.cached(0).acquire.valid := Bool(false)
-  io.cached(0).grant.ready := Bool(false)
-  io.cached(0).probe.ready := Bool(false)
-  io.cached(0).release.valid := Bool(false)
-
-  assert(!io.cached(0).probe.valid, "Shouldn't be receiving probes")
+  io.cached(0) <> Module(new DummyCache).io
 
   val all_done = gen_finished.reduce(_ && _)